[hpc-announce] [CFP] [EXTENDED_DEADLINE] DRMEC at HPCS2019 (International Workshop on Dependable and Resilient Many-Core and Exascale Computing)

[Thomas Ropars]

## CALL FOR PAPERS
[We apologize if you receive multiple copies of this CFP]

11th International Workshop on Dependable and Resilient Many-Core and 
Exascale Computing (DRMEC 2019: 
http://hpcs2019.cisedu.info/2-conference/workshops/workshop01-drmc)

Organized as part of the 17th International Conference on High 
Performance Computing & Simulation (HPCS 2019: 
http://hpcs2019.cisedu.info/home)

### Important dates:
* Paper Submission Deadline: April 8, 2019. [Last extension]
* Acceptance Notification: April 22, 2019.
* Conference Dates: July 15 - 19, 2019.

### Scope
Computing systems with a large number of processing units are 
increasingly common, both in the form of processors employing multiple 
execution cores (e.g., multi-core CPUs, GPUs, accelerators), or 
computing clusters with a large number of nodes. These many-core 
architectures bring up new capabilities, opportunities, as well as 
challenges. As the number of cores increases, so does the probability to 
have faults, both due to hardware issues (e.g., physical defects 
introduced during fabrication), software problems (e.g., a single 
crashed process bringing down the whole computation) or communication 
issues in the network infrastructure. The same can be said about the 
anticipated exascale computing systems.

This workshop focuses on software and/or hardware solutions to 
dependability, resilience, and fault-tolerance in multi- and many-core 
systems as well as in exascale computing.

Topics of interest include, but are not limited to:

* Dependable, Fault-Tolerant and resilient Many-Core Design
* Hardware and Software Debug Facilities
* Many-Core Programming and Optimization for Dependability
* Formal Techniques for Dependable HW/SW Design
* Fault-tolerant Many-Core Runtime Systems
* Fault-tolerant Programming Models for Many-Core Systems
* Case Studies of HW/SW failures in Many-Core systems
* Silent Error Detection and Mitigation in Many-Core Systems
* Solutions Based on Non-Volatile Memory for Many-Core Dependability
* Dependability, Resilience and Fault Tolerance in Exascale Systems
* Virtualization/Containers for Dependability
* Fault-Tolerant HW/SW Co-Design
* Algorithmic-based Fault Tolerance for Many-Core systems
* System-level Approaches to Error Detection and Fault Tolerance at 
Large Scale

### Instructions for paper submission

- Paper submissions must be in PDF format and should not exceed 8 
double-column pages (including references).
- Short papers (up to 4 pages), poster papers and posters (please refer 
to 
http://hpcs2019.cisedu.info/1-call-for-papers-and-participation/call-for-posters 
for posters submission details) will also be considered.

Accepted papers will be published in the Conference proceedings.

### Organization Committee
- Leonardo Bautista-Gomez, BSC
- Esteban Meneses, CeNAT & TEC
- Thomas Ropars, UGA

### Program Committee

- Max Baird, Heriot-Watt University.
- Prasanna Balaprakash, MCS Division, Argonne National Laboratory.
- Julien Bigot, Maison de la Simulation, CEA.
- Amina Guermouche, Telecom Sud-Paris.
- Ignacio Laguna, Lawrence Livermore National Laboratory.
- Nuria Losada, Universidade da Coruña.
- Harshitha Menon, Lawrence Livermore National Lab.
- Xiang Ni, University of Illinois Urbana Champaign.
- Konstantinos Parasyris, Barcelona Supercomputing Center.
- Laércio L. Pilla, LRI, Univ. Paris-Sud - CNRS.