[hpc-announce] CfP: 5th Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2019) at SC19: Submission Deadline Aug. 15

[BAKOS, JASON]

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** Call for Papers **
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Fifth International Workshop on
Heterogeneous High-performance Reconfigurable Computing (H^2RC 2019)
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Held in conjunction with Supercomputing 2019
and
In cooperation with the
IEEE Technical Consortium on High Performance Computing (TCHPC)
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Sunday, November 17, 2019 (ALL DAY)
Denver, CO
http://h2rc.cse.sc.edu
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Submission Deadline:
August 15, 2019 (4- and 8- page papers)
Accepted 8-page manuscripts published/archived by IEEE
(See below for descriptions of submission tracks.)
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As conventional von-Neumann architectures are suffering from rising power
densities, we are facing an era with power, energy efficiency, and cooling
as first-class constraints for scalable HPC. FPGAs can tailor the hardware
to the application, avoiding overheads and achieving higher hardware
efficiency than general-purpose architectures. Leading FPGA manufacturers
have recently made a concerted effort to provide a range of higher-level,
easier-to-use high-level programming models for FPGAs, and much of the
work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC
community around the potential advantages of FPGAs over other architectures.
With this in mind, this workshop, now in its fifth year, brings together
HPC and heterogeneous-computing researchers to demonstrate and share
experiences on how newly-available high-level programming models, including
OpenCL, are already empowering HPC software developers to directly leverage
FPGAs, and to identify future opportunities and needs for research in this
area.
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Submission Tracks and Contribution Selection
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Submissions are solicited for two tracks:
Track 1:  Full-length papers (8 pages) for 25-minute oral
presentation and publication in proceedings archived by IEEE.
Track 2:  Extended abstracts (4 pages) for 15-minute oral presentation
without publication.

Track 1 is targeted for technical papers containing a high level of
implementation detail and analysis discussion of experimental results.
Track 1 is suited for members of the academic and national lab community who
prefer to have their work peer-reviewed, indexed and archived by IEEE.

Track 2 is targeted for industrial contributions that describe new
capabilities
and opportunities offered by emerging technologies and products or work in
progress presentations by the academic and national lab community. The
emphasis of this track is to initiate a discussion with the audience.

All submissions are reviewed and evaluated by at least three members of our
technical program committee.  From the TPC evaluation of each
submission, the
organizing committee will select papers for presentation based on a criteria
that is equally weighted between scientific merit and level of interest and
relevance to the HPC community.
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Topics
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1. Improvement of performance or efficiency of HPC or data center
applications with FPGAs
2. System integration of FPGAs in clouds and HPC systems
3. Leveraging reconfigurability
4. Benchmarks
6. Programming languages, tools, and frameworks
7. Future-gazing
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Important dates:
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Submission Deadline: August 15, 2019
Acceptance Notification: September 15, 2019
Camera-ready Manuscripts Due: October 11, 2019
Workshop Date: November 17, 2019
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Organizing Committee:
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Jason D. Bakos, University of South Carolina
Michaela Blott, Xilinx
Franck Cappello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Christian Plessl, Paderborn University, Germany

-- 
Jason D. Bakos, Ph.D.
Professor
Dept. of Computer Science and Engineering
Univ. of South Carolina
301 Main St., Suite 3A01L
Columbia, SC 29208
803-777-8627 (voice), 803-777-3767 (fax)
http://www.cse.sc.edu/~jbakos
jbakos at cse.sc.edu