[hpc-announce] [CFP] GrAPL 2019 - co-located with IPDPS 2019

Tumeo, Antonino Antonino.Tumeo at pnnl.gov
Wed Jan 2 04:55:45 CST 2019

[Apologies if you receive multiple copies of this CFP]

GrAPL 2019: Workshop on Graphs, Architectures, Programming, and Learning
Co-Located with IPDPS 2019
May 20, 2019
Hilton Rio De Janeiro

GrAPL is the result of the combination of two IPDPS workshops:
GABB: Graph Algorithms Building Blocks
GraML: Workshop on The Intersection of Graph Algorithms and Machine Learning

Data analytics is one of the fastest growing segments of computer science. Much of the recent focus in Data Analytics has emphasized machine learning. This is understandable given the success of deep learning over the last decade. However, many real-world analytic workloads are a mix of graph and machine learning methods. Graphs play an important role in the synthesis and analysis of relationships and organizational structures, furthering the ability of machine-learning methods to identify signature features. Given the difference in the parallel execution models of graph algorithms and machine learning methods, current tools, runtime systems, and architectures do not deliver consistently good performance across data analysis workflows.  In this workshop we are interested in Graphs, how their synthesis (representation) and analysis is supported in hardware and software, and the ways graph algorithms interact with machine learning. The workshop’s scope is broad which is a natural outgrowth of the wide range of methods used in large-scale data analytics workflows. 

The objectives of this workshop are as follows:
* Understand data analytics workflows and the mix of graph and machine learning algorithms they require
* Understand the synergies between evolving device technology and graph analytics applications to drive: 1) the direction of emerging hardware and software architecture, 2) new graph analytics algorithms that better exploit the emerging hardware; and 3) application workflows that mix the large graph synthesis and analytics and machine learning.
* Explore different frameworks, languages and libraries to support programming graph analytics and machine learning algorithms
* Evaluate the performance and scalability of integrated platforms for large graph synthesis and analysis, and machine learning

While each of these topics on their own are well addressed in other workshops, we are particularly interested in the cross-cutting synergies. For example, hardware and software architectures specialized for machine learning (and in particular deep learning) may be poorly suited for graph algorithms. Can we understand these conflicting needs and perhaps find an architecture jointly optimized for both?

This workshop seeks papers on the theory, model-based analysis, simulation, and analysis of operational data for graph analytics and related machine learning applications. We are particularly interested in papers that:

* Discuss hardware platforms specialized for addressing large, dynamic, multi-attributed graphs and associated machine learning;
* Discuss programming models and associated frameworks such as Pregel, Galois, Boost, GraphBLAS, GraphChi, etc., for building large multi-attributed graphs;
* Discuss how frameworks for building graph algorithms interact with those for building machine learning algorithms;
* Discuss the problem domains and problems addressable with graph methods, machine learning methods, or both;
* Provide tractability performance analysis in terms of complexity, time-to-solution, problem size, and quality of solution for systems that deal with mixed data analytics workflows.

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. 

Important Dates
Position or full paper submission: February 1, 2019 
Notification: February 28, 2019
Camera-ready: March 15, 2019
Workshop: May 20, 2019

Submission site: https://easychair.org/conferences/?conf=grapl2019

Submitted manuscripts may not exceed ten (10) pages, single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. 

The templates are available at: 

General co-Chairs

Tim Mattson (Intel), timothy.g.mattson at intel.com
Antonino Tumeo (PNNL), antonino.tumeo at pnnl.gov

Program co-Chairs

Ananth Kalyanaraman (WSU), ananth at wsu.edu
Manoj Kumar (IBM), manoj1 at us.ibm.com

Steering Committe

David A. Bader (Georgia Institute of Technology)
Aydın Buluç (LBNL)
John Feo (PNNL)
John Gilbert (UC Santa Barbara)
Mahantesh Halappanavar (PNNL)
Jeremy Kepner (MIT Lincoln Laboratory)

Technical Program Committee

Aydin Buluç, LBNL, US
Timothy A. Davis, University of Florida, US
Jana Doppa, Washington State University, US
John Gilbert, University of California at Santa Barbara, US
Oded Green, Georgia Institute of Technology & NVIDIA, US
Jeremy Kepner, MIT, US
Arif Khan, PNNL, US
Hao	Lu, ORNL, US
Kamesh Madduri, The Pennsylvania State University, US
Rupesh Nasre, IIT Madras, IN
John Owens, University of California, Davis, US
Arnau Prat, Universitat Politècnica de Catalunya, ES
Jason Riedy, Georgia Institute of Technology, US
P. Sadayappan, The Ohio State University, US
A. Erdem	Sarıyüce, University at Buffalo, US
Arun Sathanur, PNNL, US
Brian Van Essen, LLNL, US
Flavio Vella, Free University of Bozen, IT
Yangzihao Wang, University of California, Davis, US
Marinka Zitnik, Stanford University, US
Jaroslaw Zola, University at Buffalo, US

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