[hpc-announce] [CFP] APPMM 2019, Int. Workshop on Advances in Parallel Programming Models and Frameworks for the Multi-/Many-core Era

[Biagio Cosenza]

CALL FOR PAPERS & PARTICIPATION

The 8th International Workshop on Advances in Parallel Programming 
Models and Frameworks for the  Multi-/Many-core Era (APPMM 2019)
http://hpcs2019.cisedu.info/2-conference/workshops/workshop06-appmm

As part of The 17th International Conference on High Performance 
Computing & Simulation (HPCS 2019) http://hpcs2019.cisedu.info/ or 
http://conf.cisedu.info/rp/hpcs19

July 15 – 19, 2019
Dublin, Ireland

Paper Submission Deadline: 20 March 2019

Submissions could be for full papers, short papers, poster papers, or 
posters


SCOPE AND OBJECTIVES
With multi- and many-core based systems, performance increase on the 
microprocessor side will continue according to Moore's Law, at least in 
the near future.  However, as the number of cores and the complexity of 
on-chip memory hierarchies increases, performance limitations due to 
slow memory access are expected to get worse, making it hard for users 
to fully exploit the theoretically available performance. In addition, 
the increasingly sophisticated design of compute clusters, based on the 
use of accelerator components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, 
integrated GPUs etc.) add further challenges to achieving efficient 
programming of many-core-based HPC  and high-end embedded systems.

Therefore, compute and data intensive tasks can only benefit from the 
hardware's full potential, if both processor and architecture features 
are taken into account at all stages - from the early algorithmic 
design, via appropriate programming models, up to the final implementation.

The APPMM Workshop topics of interest include (but are not limited to) 
the following:
     - Novel programming models and associated frameworks, or extensions 
of existing programming models, to ease offloading and parallelization 
of computation to multi- and many-cores.
     - Compiler, runtime and parallelization approaches to optimally 
exploit specific features of heterogeneous hardware (e.g., hierarchical 
communication layout, NUMA, scratchpad memory, accelerators, etc.) and 
to maximize performance, energy and other relevant metrics in many-core 
operation.
     - Many-Core Architectures for emerging scientific computing 
applications
     - Architecture-assisted software design. Novel architectural 
concepts to boost software execution and to overcome scalability issues 
of current multi- and many-core systems. Hardware-assisted runtime 
environment services (e.g., synchronization, custom memory hierarchies, 
etc.)
     - Concepts for exploiting emerging vector extensions of instruction 
sets.
     - Many-core Hw/SW Design for Machine/Deep Learning processing and 
applications
     - Software engineering, code optimization, and code generation 
strategies for parallel systems with multi- and many-core processors.
     - Tools for performance and memory behavior analysis (including 
cache simulation) for parallel systems with multi- and many-core processors.
     - Performance modeling and performance engineering approaches for 
multi-thread and multi-process applications.
     - Application parallelization use cases, benchmarking and benchmark 
suites. Hardware-aware, compute- and memory-intensive simulations of 
real-world problems in computational science and engineering (for 
example, from applications in electrical, mechanical, civil, or medical 
engineering).
     - Manycore-aware approaches for large-scale parallel simulations in 
both implementation and algorithm design, including scalability studies.


INSTRUCTIONS FOR PAPER SUBMISSIONS
You are invited to submit original and unpublished research works on 
above and other topics related to Many-core computing, modeling and 
algorithms. Submitted papers must not have been published or 
simultaneously submitted elsewhere until it appears in HPCS proceedings, 
in the case of acceptance, or notified otherwise. Submission can be for
-  Regular papers, please submit a PDF copy of your full manuscript, not 
to exceed 8 double-column formatted pages per template, and include up 
to 6 keywords and an abstract of no more than 400 words. Additional 
pages will be charged additional fee. Submission should include a cover 
page with authors' names, affiliation addresses, fax numbers, phone 
numbers, and all authors email addresses. Please, indicate clearly the 
corresponding author(s) although all authors are equally responsible for 
the manuscript.
-  Short papers (up to 4 pages), please submit a PDF copy of your full 
manuscript, not to exceed 4 double-column formatted pages per template, 
and include up to 6 keywords and an abstract of no more than 400 words. 
Additional pages will be charged additional fee. Submission should 
include a cover page with authors' names, affiliation addresses, fax 
numbers, phone numbers, and all authors email addresses. Please, 
indicate clearly the corresponding author(s) although all authors are 
equally responsible for the manuscript.
-  Poster papers and Posters (please refer to 
http://hpcs2019.cisedu.info/1-call-for-papers-and-participation/call-for-posters 
for posters submission details) will also be considered.

Please specify the type of submission you have. Please include page 
numbers on all preliminary submissions to make it easier for reviewers 
to provide helpful comments.

Submit a PDF copy of your full manuscript to the Workshop paper 
submission site at https://easychair.org/conferences/?conf=appmm2019 . 
Acknowledgment will be sent within 48 hours of submission.

Conference Policies
Only PDF files will be accepted, uploaded to the submission link above. 
Each paper will receive a minimum of three reviews. Papers will be 
selected based on their originality, relevance, significance, technical 
clarity and presentation, language, and references. Submission implies 
the willingness of at least one of the authors to register and present 
the paper, if accepted. At least one of the authors of each accepted 
paper will have to register and attend the HPCS 2019 conference to 
present the paper at the Workshop as scheduled. By submitting the paper 
to the HPCS conference, all authors agree to abide by all HPCS 
conference paper submission, publication and presentation policies as 
well as following ethical and professional codes of conduct, including 
those of the professional co-sponsoring organizations. For more 
information, please refer to the Authors Info and Registration Info pages.

Proceedings
Accepted papers will be published in the Conference proceedings. 
Instructions for final manuscript format and requirements will be posted 
on the HPCS 2019 Conference web site. It is our intent to have the 
proceedings formally published in hard and soft copies and be available 
at the time of the conference. The proceedings is projected to be 
included in the IEEE or ACM Digital Library and indexed in all major 
indexing services accordingly.

SPECIAL ISSUE
Plans are underway to have the best papers, in extended version, 
selected for possible publication in a reputable journal as special 
issue. Detailed information will soon be announced and will be made 
available on the conference website.

If you have any questions about paper submission or the Workshop, please 
contact the workshop organizers.

IMPORTANT DATES
     Paper Submissions: ---------------------------------- 20 March 2019
     Acceptance Notification: ---------------------------- 08 April 2019
     Camera Ready Papers and Registration Due by: -------- 24 April 2019
     Conference Dates:  -------------------------------- 15–19 July 2019


WORKSHOP ORGANIZERS

Ben Juurlink (general chair)
     Institut für Technische Informatik und Mikroelektronik (TIME)
     Technische Universität Berlin, Berlin, Germany
     Phone: +49 (0)30 314 73 130

Giuseppe Tagliavini  (TPC co-chair)
     Dipartimento di Ingegneria dell'Energia Elettrica e 
dell'Informazione "Guglielmo Marconi"
     University of Bologna, Bologna, Italy
     Phone: +39 051 20 9 2757
     Email: giuseppe.tagliavini at unibo.it

Biagio Cosenza (publicity and web chair)
    Embedded Systems Architecture(AES) Group
    Technische Universität Berlin, Berlin, Germany
    Phone: +49 (0)30 314 24 294
    Email: cosenza at tu-berlin.de

Jeronimo Castrillon  (TPC co-chair)
    Center for Advancing Electronics Dresden (CFAED)
    Technische Universität Dresden, Dresden, Germany
    Phone: +49 (0)351 463 42 716
    Email: jeronimo.castrillon at tu-dresden.de


International Program Committee*:
All submitted papers will be rigorously reviewed by the workshop 
technical program committee members following similar criteria used in 
HPCS 2019 and will be published as part of the HPCS 2019 Proceedings.

     Nicola Bombieri,  University of Verona, Italy
     Paolo Burgio, University of Modena and Reggio Emilia
     Roberto Giorgi, University of Siena
     Diana Göhringer, TU Dresden
     Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg
     Jörg Keller,  FernUniversität in Hagen
     Georgios Keramidas, Think Silicon
     Christoph Kessler, Linköping University
     Christian Pinto, IBM Research Ireland
     Cristina Silvano, Politecnico di Milano
     Nicolai Stawinoga, Imperial College London

(* Committee formation is pending and will be finalized shortly.)


All submitted papers will be rigorously reviewed by the workshop 
technical program committee members following similar criteria used in 
HPCS 2019 and will be published as part of the HPCS 2019 Proceedings.

For information or questions about Conference's paper submission, 
tutorials, posters, workshops, special sessions, exhibits, demos, panels 
and forums organization, doctoral colloquium, and any other information 
about the conference location, registration, paper formatting, etc., 
please consult the Conference’s web site at URL: 
http://hpcs2019.cisedu.info/  or  http://conf.cisedu.info/rp/hpcs19 or 
contact one of the Conference's organizers.

Thanks very much for your cooperation,
Ben Juurlink, Giuseppe Tagliavini, Jeronimo Castrillon, and Biagio Cosenza