[hpc-announce] IEEE/ACM NOCS 2019: Call for Participation

Tue Aug 27 06:59:14 CDT 2019

**Apologies if you received multiple copies of this email**

13th IEEE/ACM International Symposium on Networks-on-Chip
Oct 17-18, 2019; co-located with ESWEEK 2019, New York, NY, USA
https://www.engr.colostate.edu/nocs2019/

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

Registration for NOCS 2019 is open at: https://esweek.org/registration

The conference program includes several keynotes, tutorials, special sessions and regular paper session with participants from industry and academia. We hope you are able to attend!

Preliminary Program Schedule
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THURSDAY OCTOBER 17, 2019

[09:00 - 09:15] Opening Remarks

[09:15 - 10:15] Keynote 1
Session chair: Sudeep Pasricha, Colorado State University

Interconnect Meets Architecture: On-Chip Communication in the Age of Heterogeneity
Partha Pratim Pande, Washington State University

[10:15 - 10:45] Coffee Break

[10:45 - 12:00] Regular Paper Session I: NoC and Router Design
Session chair: Andreas Herkersdorf, Technical University of Munich

UBERNoC: Unified Buffer Energy-Efficient Router for Network-on-Chip
Hossein Farrokhbakht, Henry Kao and Natalie Enright Jerger, University of Toronto

Ghost Routers: Energy-Efficient Asymmetric Multicore Processors with Symmetric NoCs
Hyojun Son, KAIST, Hanjoon Kim, Furiosa A.I., Hao Wang, University of Wisconsin-Madison, Nam Sung Kim, Samsung Electronics, and John Kim, KAIST

BINDU: Deadlock-Freedom with One Bubble in the Network
Mayank Parasar and Tushar Krishna, Georgia Institute of Technology

[12:00 - 12:30] Invited Talk
Session Chair: Ajay Joshi, Boston University

Accelerator Fabric in Facebook Zion Training System
John Kim, KAIST/Facebook

[12:30 - 14:00] Lunch

[14:00 - 15:15] Special Session 1: Interconnection Networks for Deep Neural Networks
Session chair: Tushar Krishna, Georgia Institute of Technology
Session organizers: Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology

NoC-based DNN Accelerator: A Future Design Paradigm
Kun-Chih Chen, National Sun Yat-sen University, Masoumeh Ebrahimi, KTH Royal Institute of Technology, Ting-Yi Wang, National Sun Yat-sen University, and Yuch-Chi Yang, National Sun Yat-sen University

Energy-Efficient and High-Performance NoC Architecture and Mapping Solution for Deep Neural Networks
Md Farhadur Reza and Paul Ampadu, Virginia Polytechnic Institute and State University

Flow mapping and data distributing on mesh-based deep learning accelerator
Seyedeh Yasaman Hosseini Mirmahaleh, Islamic Azad University Tehran, Midia Reshadi, Islamic Azad University Tehran, Hesam Shabani, Lehigh University, Xiaochen Guo, Lehigh University, and Nader Bagherzadeh, University of California, Irvine

[15:15 - 15:30] Lightening Talks for Work in Progress (WIP) Posters
Session chair: Sudeep Pasricha, Colorado State University

Reinforcement Learning based Interconnection Routing and Adaptive Traffic Optimization
Sheng-Chun Kao, Georgia Institute of Technology, Chao-Han Huck Yang, Georgia Institute of Technology, Pin-Yu Chen, IBM Watson AI Foundation Group, Xiaoli Ma, Georgia Institute of Technology, and Tushar Krishna, Georgia Institute of Technology.

Power efficient Photonic Network-on-Chip for a Scalable GPU
Janibul Bashir, Khushal Sethi and Smruti R. Sarangi, Indian Institute of Technology, Delhi

CDMA-based Multiple Multicast Communications on WiNOC for efficient parallel computing
Navonil Chatterjee, Lab-STICC, Université Bretagne Sud, Hemanta Kumar Mondal, NIT Durgapur, Rodrigo Cataldo, Lab-STICC, Université Bretagne Sud, and Jean-Philippe Diguet, Lab-STICC, Université Bretagne Sud

Channel Mapping Strategies for Effective Protection Switching in Fail-Operational Hard Real-Time NoCs
Max Koenen, Nguyen Anh Vu Doan, Thomas Wild and Andreas Herkersdorf, Technical University of Munich

Multi-Carrier Direct Sequence Spread Spectrum Transceiver for WiNoC
Joel Ortiz Sosa, Univ. Rennes, Inria, Olivier Sentieys, Univ. Rennes, Inria, Christian Roland, Lab-STICC, Université Bretagne Sud, and Cedric Killian, Univ. Rennes, Inria

Detection and Prevention Protocol for Black Hole Attack in Network-on-Chip
Luka Daoud and Nader Rafla, Boise State University

Analyzing Networks-on-Chip based Deep Neural Networks
Maurizio Palesi, University of Catania, Giuseppe Ascia, University of Catania, Davide Patti, University of Catania, Salvatore Monteleone, University of Catania, Vincenzo Catania, University of Catania, and John Jose, Indian Institute of Technology Guwahati.

[15:30 - 16:15] WIP Posters and Coffee Break

[16:15 - 17:30] Regular Paper Session 2: Best Paper Nominees
Session chair: Paul Ampadu, Virginia Polytechnic Institute and State University

NoC-enabled Software/Hardware Co-Design Framework for Accelerating k-mer Counting
Biresh Kumar Joardar, Washington State University, Priyanka Ghosh, Washington State University, Partha Pratim Pande, Washington State University, Ananth Kalyanaraman, Washington State University, and Sriram Krishnamoorthy, Pacific Northwest National Laboratory

SMART++: Reducing cost and improving efficiency of multi-hop bypass in NoC routers
Iván Pérez, Enrique Vallejo and Ramón Beivide, University of Cantabria, Santander

APEC: Improved Acknowledgement Prioritization through Erasure Coding in Bufferless NoCs
Michael Vonbun, Adrian Schiechel, Nguyen Anh Vu Doan, Thomas Wild and Andreas Herkersdorf, Technical University of Munich

[19:00 - 21:00] Dinner (TBD)

FRIDAY OCTOBER 18, 2019

[09:00 - 10:00] Keynote 2
Session chair: Ajay Joshi, Boston University

Toward Fast Analysis and Exploration of Communication Fabrics
Raid Ayoub, Intel

[10:00 - 10:15] Coffee Break

[10:15 - 11:30] Tutorial 1: System on Package (SoP): A Holistic Approach for System Integration
Session chair: Tushar Krishna, Georgia Institute of Technology

Speakers: Madhavan Swaminathan, Mohan Kathaperumal, Georgia Institute of Technology

[11:30 - 12:30] Tutorial 2: High Performance Networks
Session chair: Ishan Thakkar, University of Kentucky

Engineering a specialized, high-performance network
Brian Towles, Brian Greskamp, D.E. Shaw Research

[12:30 - 14:00] Lunch

[14:00 - 15:40] Regular Paper Session 3: NoC Potpourri
Session chair: Maurizio Palesi, University of Catania

ClusCross: A New Topology for Silicon Interposer-Based Network-on-Chip
Hesam Shabani and Xiaochen Guo, Lehigh University

Distributed SDN Architecture for NoC-based Many-core SoCs
Marcelo Ruaro, PUCRS, Nedison Velloso, PUCRS, Axel Jantsch, TU Wien, Vienna, and Fernando Moraes, PUCRS

Approximate Nanophotonic Interconnects
Jaechul Lee, Univ Rennes, Inria, Cédric Killian, Univ Rennes, Inria, Sébastien Le Beux, Concordia University, and Daniel Chillet, Univ Rennes, Inria

Direct-Modulated Optical Networks for Interposer Systems
Mohammad Reza Jokar, University of Chicago, Lunkai Zhang, University of Chicago, John M. Dallesasse, University of Illinois at Urbana-Champaign, Frederic T. Chong, University of Chicago and Yanjing Li, University of Chicago

[15:40 - 16:00] Coffee Break

[16:00 - 17:15] Special Session 2: Heterogeneous Integration and Interconnect Fabrics
Session chair: Ishan Thakkar, University of Kentucky
Session organizers: Baris Taskin, Drexel University, Boris Vaisband, McGill University

3D NoCs with Active Interposer for Multi-Chip Module
Vasil Pano, Ragh Kuttappa and Baris Taskin, Drexel University

Global and Semi-Global Communication on Silicon Interconnect Fabric
Boris Vaisband and Subramanian Iyer, University of California, Los Angeles

A 7.5-mW 10-Gb/s 16-QAM Wireline Transceiver with Carrier Synchronization and Threshold Calibration for Mobile Inter-chip Communications in 16-nm FinFET
Jieqiong Du, University of California, Los Angeles, Chien-Heng Wong, University of California, Los Angeles, Yo-Hao Tu, National Central University, Wei-Han Cho, University of California, Los Angeles, Yilei Li, University of California, Los Angeles, Yuan Du, University of California, Los Angeles, Po-Tsang Huang, National Chiao Tung University, Sheau-Jiung Lee, TSVLink Corp, and Mau-Chang Frank Chang, University of California, Los Angeles.

[17:15 - 17:30] Closing Remarks with Best Paper Announcement