[hpc-announce] Call for Papers: FPGA 2019 -- Submission deadline extended to Oct 1st
jli at ece.wisc.edu
Tue Sep 18 18:05:46 CDT 2018
Call for Papers: FPGA 2019
Twenty-Seventh ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
FPGA 2019. 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. February 24 - 26, 2019. Embassy Suites by Hilton Monterey Bay Seaside, Seaside, California
February 24-26, 2019
Embassy Suites by Hilton Monterey Bay Seaside
1441 Canyon Del Rey, Seaside, California, 93955, USA
Submission Deadline: October 1st, 2018
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2019) is the premier conference for presentation of advances in FPGA technology. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library.
Types of Submissions Sought
1. Research Papers
As usual, we solicit research papers related to the following areas:
* FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
* FPGA Circuit Design: Circuits and layout techniques for design of FPGAs. Impact of future process and design technologies on FPGAs. Methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability. Use of novel memory or nano-scale devices in FPGAs.
* CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
* High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
* FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable computing, adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
* Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, efficiency, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.
Research submissions may be either:
* Full: at most 10 pages, for a full presentation at the conference; or
* Short: at most 6 pages, for a brief presentation.
A paper submitted as either full or short will only be considered in that category.
2. Tutorial Papers on Emerging Applications / Methodologies
The conference will include a Sunday workshop is oriented toward users of FPGAs: be it deep learning implementations, computer security or other emerging topics of interest. For this category, we solicit tutorial papers describing effective design techniques and design flows. The ideal submission will enable beginning researchers to enter the area, current researchers to broaden their scope, and practitioners to gain new and applicable skills. Tutorial submissions need not present novel research results, but should integrate expert practical and/or research knowledge related to FPGAs for a broader audience. This may include:
* Technical descriptions of new commercial or academic design tools of general interest;
* Insightful summaries of the state-of-the-art that suggest open research problems; and
* In-depth design tutorials and design experiences.
Tutorial submissions should be at least 4 and at most 10 pages. Accepted submissions will be published in the proceedings and allocated a presentation time of up to one hour, appropriate to the content.
3. Panel Discussion Proposals
We also solicit proposals for the panel discussion at the conference banquet. The submission should outline the topic, questions to be addressed, and suggested speakers.
Submissions of all types should be made in the form of an English language PDF file, on-line at https://www.softconf.com/i/fpga2019
. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/
. Submissions must be received by September 16, 2018 at 11:59 PM (in any time zone).
Submissions will be considered for acceptance as full or short regular papers, workshop papers, or posters. Regular submissions related to the workshop topic may be scheduled for presentation during the workshop. Regular or workshop submissions will also be considered for acceptance as a poster. A paper submitted to the short or full paper category will only be considered in that category.
The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. Exceptions may be allowed, with prior approval of the Program Chair, in cases where the authors' identity is vital to evaluating the paper (e.g., papers presenting updates of infrastructure used by the FPGA community). References to the authors' prior work should be made in the 3rd person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as "Removed for blind review", but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission.
September 16, 2018
Notification of acceptance:
Camera-ready copy of accepted papers due:
Early December, 2018
* General Chair: Kia Bazargan<http://umn.edu/~kia>, University of Minnesota, generalchair at isfpga.org<mailto:generalchair at isfpga.org>.
* Program Chair: Stephen Neuendorffer<https://sites.google.com/site/sneuendorffer/>, Xilinx, programchair at isfpga.org<mailto:programchair at isfpga.org> .
* Finance Chair: Jason H. Anderson<http://janders.eecg.toronto.edu/>, University of Toronto, financechair at isfpga.org<mailto:financechair at isfpga.org>
* Publicity Chair: Jing Li<https://wicil.ece.wisc.edu/jli/>, University of Wisconsin-Madison, publicitychair at isfpga.org<mailto:publicitychair at isfpga.org>
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