[hpc-announce] Call for Papers: Second Workshop on “Software Challenges to Exascale Computing (SCEC 2018)

Wed Sep 5 12:52:30 CDT 2018

========================= Call For Papers (CFP) =====================================

Second Workshop on “Software Challenges to Exascale Computing (SCEC 2018)”
Delhi, India, December 13-14, 2018
https://scec18.github.io/

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Overview

Supercomputers are used to power discoveries and to reduce the time-to-results in a wide variety of disciplines such as engineering, physical sciences, and healthcare. They are globally considered as vital for staying competitive in defense, research and development activities in various disciplines, financial sector, several mainstream businesses and even agriculture. An integral requirement for enabling the usage of the supercomputers, like any other computer, is the availability of the software. Scalable and efficient software is typically required for optimally using the large-scale supercomputing platforms, and thereby, effectively leveraging the investments in the advanced CyberInfrastructure (CI). However, developing and maintaining such software is challenging due to several factors, such as, 1) no well-defined processes or guidelines for writing the software that can ensure high-performance on supercomputers, and 2) shortfall of trained workforce having skills in both software engineering and supercomputing. With the rapid advancement in the computer architecture discipline, the complexity of the processors that are used in the supercomputers is also increasing, and, in turn, the task of developing efficient software for supercomputers is further becoming challenging and complex. To mitigate such challenges, there is a need for a common platform that brings together the different stakeholders from High Performance Computing (HPC) and software engineering domains. To provide such a platform, the second workshop on "Software Challenges to Exascale Computing (SCEC)" is being organized in Delhi, India, in December 2018.

Topics of interest for the SCEC 2018 workshop include, but are not limited to:

  *   Tools and techniques for code modernization
  *   Generative programming techniques in HPC
  *   Supporting software and middleware for HPC environments: e.g., MPI libraries
  *   Tools for profiling, debugging, and parallelizing applications
  *   Tools and techniques for memory and power optimization
  *   Large-scale HPC applications (tuning, optimization, and implementation on HPC resources)
  *   HPC Science Gateways, Containerization (HPC in the Cloud)
  *   Fault-tolerance
  *   Filesystems and Parallel I/O
  *   High-level interfaces, libraries, compilers, and runtime systems for parallel programming
  *   Domain-Specific Languages in HPC
  *   Best practices for HPC software development

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Student Travel Award

The SCEC18 workshop has limited amount of funds available to cover the workshop participation cost for undergraduate/graduate students from the U.S. based institutions. Additional information on the student travel grant is available on the workshop website.

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Paper Preparation Guidelines, and Review Process

The workshop proceedings will be published by Springer-Verlag.

We invite authors to submit their original and unpublished work, that is not under review for another publication. Full papers (10 -15 pages in length including references) should be formatted as per the Springer-specified guidelines (details below) for the double-blind review.

We also invite short papers or extended abstracts for lightning talks. The short papers should also be prepared following the Springer guidelines, and could be 5-8 pages in length including references. However, these short papers will NOT be published in the proceedings but will be archived and made publicly accessible through Figshare and a Github repo. These submissions will have a DOI number for future citations. Those interested in presenting lightning talks are also required to submit the PDF copies of the rough draft of their slides. The PDF of each abstract and the associated slides can be merged into a single PDF file and submitted for peer-review.

The PDF version of the papers/extended abstracts can be submitted for review through the SCEC 2018 submission system that is set-up using Easychair: https://easychair.org/conferences/?conf=scec2018

Springer's formatting information is available at the following link:
https://www.springer.com/us/computer-science/lncs/conference-proceedings-guidelines

The review process is double-blind, and each paper will be reviewed by at least three committee members and/or external reviewers. The papers will be evaluated on the basis of the relevance to the workshop theme, clarity of the content presented, originality of the work, and the impact of the work on the community.

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Deadlines

Paper submission deadline: October 1, 2018

Notifications of acceptance/rejection sent by: November 1, 2018

Camera-ready copies of accepted papers due on:  November 10, 2018

At least one author of each accepted paper should register for the workshop by: November 25, 2018

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Organizing Committee
Amitava Majumdar, San Diego Supercomputing Center (SDSC), UC San Diego, La Jolla, USA (General Co-Chair)
Ritu Arora, Texas Advanced Computing Center (TACC), UT Austin, Austin, USA (General Co-Chair)
Sharda Dixit, Centre of Development of Advanced Computing (C-DAC), Pune, India (Program Co-Chair)
Anil Kumar Gupta, C-DAC, Pune, India (Program Co-Chair)
Vinai Kumar Singh, Indraprastha Engineering College, Ghaziabad, India (Logistics and Finance Chair)
Manu Awasthi, IIT-Gandhinagar, Gandhinagar, India (Communications Co-Chair)
Venkatesh Shenoi, C-DAC, Pune, India (Communications Co-Chair)
Vinodh Kumar Markapuram,  C-DAC, Pune, India

Technical Program Committee
Amit Ruhela, Ohio State University, Ohio, USA
Amitava Majumdar, San Diego Supercomputing Center (SDSC), UC San Diego, La Jolla, USA
Anil Kumar Gupta, C-DAC, Pune, India
Anirban Jana, Pittsburgh Supercomputing Center (PSC), Pittsburg, USA
Aniruddha Gokhale, Vanderbilt University, Tennessee, USA
Antonio Gomez, Intel, Hillsboro, Oregon, USA
Amarjeet Sharma,  C-DAC, Pune, India
Damon McDougall, Texas Advanced Computing Center (TACC), UT Austin, Austin, USA
Devangi Parikh, University of Texas at Austin, Austin, Texas, USA
Dinesh Rajagopal, BULL/AtoS, Bangalore, India
Galen Arnold, National Center of Supercomputing Applications, Illinois, USA
Hari Subramoni, Ohio State University, Ohio, USA
Krishna Muriki, Lawrence Berkeley National Laboratory, California, USA
Lars Koesterke, Texas Advanced Computing Center, UT Austin, Austin, USA
Manu Awasthi, IIT-Gandhinagar, Gandhinagar, India
Mahidhar Tatineni, San Diego Supercomputer Center, (SDSC), UC San Diego, La Jolla, USA
Milind Jagtap, Center of Development of Advanced Computing (C-DAC), Pune, India
Nisha Agarwal, Center of Development of Advanced Computing (C-DAC), Pune, India
Purushotham Bangalore, University of Alabama at Birmingham, Alabama, USA
Ritu Arora, Texas Advanced Computing Center (TACC), UT Austin, Austin, USA
Robert Sinkovits, San Diego Supercomputing Center (SDSC), UC San Diego, La Jolla, USA
Sandeep Joshi, CDAC, Pune, India
Sharda Dixit, Center of Development of Advanced Computing (C-DAC), Pune, India
Si Liu, Texas Advanced Computing Center, UT Austin, Austin, USA
Soham Ghosh, Intel, India
Subhashini Sivagnanam, San Diego Supercomputer Center, (SDSC), UC San Diego, La Jolla, USA
Sukrit Sondhi, Fulcrum Worldwide, NJ, USA
Suresh Marru, Indiana University Bloomington, Indiana, USA
Tajendra Singh, University of California, Los Angeles (UCLA), California, USA
Venkatesh Shenoi, C-DAC, Pune, India
Victor Eijkhout, Texas Advanced Computing Center, UT Austin, Austin, USA
Vinai Kumar Singh, Indraprastha Engineering College, Ghaziabad, India

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