[hpc-announce] CfP: Journal of Supercomputing S.I. : Vector Architectures and Applications in the Exascale Era

Juan Manuel Cebrián González jm.cebriangonzalez at gmail.com
Mon Oct 15 06:13:45 CDT 2018

Apologies if you got multiple copies of this email.


Vector architectures have been present almost since the beginning of
the history of supercomputing. These architectures are able to
represent an operation over several data elements with a single
instruction, exploiting data-level parallelism (DLP). Data-level
parallelism coupled with thread-level parallelism (TLP) are keystones
to achieve Exascale computing under a reasonable power budget. DLP and
TLP are present in most modern supercomputers, regardless of being
based on accelerators (e.g., GPGPUs) and/or CPUs (IBM Vector Media
eXtension –VMX–, NEC SX architecture, Intel Advanced Vector eXtension
–AVX– and ARM Scalable Vector Extension –SVE–).

Since most general purpose architectures are embracing vector based
designs, designers, programming models and languages, tools and
libraries must adapt to take full advantage of the features available
in vector architectures. This special issue is looking for original
research works to explore the intersection between both algorithm
design and hardware improvements to deal with the emergent challenges
of the upcoming vector applications. In this regard, one of the main
objectives of this special issue is discussing about the main trends
in vector parallel processing, algorithm definition and problem-domain
requirements altogether, which may anticipate future solutions to be
translated into real benefits to the society.


The goal of this special issue is to present the readers with novel
hardware enhancements, vectorization tools, codes and strategies as
well as current (and future) trends in vector architectures. Our goal
is to cover the full development stack, from applications to hardware.
The target audience will be application developers as well as academy
and industry researchers interested in improving vector codes and
vector architectures. Topics of interest, of both theoretical and
practical significance, include but are not limited to vector:

- Programming framework
- Programming model and language explorations
- Compilation and optimization - including algorithmic improvements
and code optimization
- Performance Analysis and Debugging Tools
- Performance Metrics and Evaluations
- Libraries and run-time systems
- Design, generation, verification and validation of representative applications
- Case-studies of representative applications
- Innovative applications for vector architectures
- Hardware studies and micro-architectural implementation tradeoffs

Important Dates

- Submission Due November 30, 2018

Information for Authors

VAAEE Special Issue will follow the Journal of Supercomputing format
templates available here

Each article must not exceed 18 pages following the aforementioned
template, including references.

Please check further details about Information for Authors at JSC
webpage (https://www.springer.com/computer/swe/journal/11227).

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