[hpc-announce] FPGA high-level synthesis tutorial at SC18 - Call for Participation

Torsten Hoefler htor at inf.ethz.ch
Thu Oct 11 00:19:18 CDT 2018

==== CALL FOR PARTICIPATION ================

Your are hereby cordially invited to our tutorial on:

**Productive parallel programming for FPGA with high-level synthesis**

Johannes de Fine Licht and Torsten Hoefler

The International Conference for High Performance Computing, Networking, 
Storage, and Analysis 2018 [SC'18]

Sunday November 11th, 13:30 - 17:00
Room C144

All information can be found on our website 

As the scale of large high performance computing systems increases, so 
does their power consumption, making energy efficiency a first class 
citizen in their design. While GPUs and custom processors have improved 
this situation significantly, reconfigurable architectures, such as 
FPGAs, promise another major step in energy efficiency, constituting a 
middle ground between fixed hardware architectures and custom-built 
ASICs. Programming FPGAs has traditionally been done in hardware 
description languages, requiring extensive hardware knowledge and 
significant engineering effort. This tutorial shows how high-level 
synthesis (HLS) can be harnessed to productively achieve scalable 
pipeline parallelism on FPGAs. Attendees will learn how to target FPGA 
resources from high-level C++ or OpenCL code, guiding the mapping from 
imperative code to hardware, enabling them to develop massively parallel 
designs with real performance benefits. We treat concrete examples well 
known from the software world, relating traditional code optimizations 
to both corresponding and new transformations for hardware, building on 
existing knowledge when introducing new topics. By bridging the gap 
between software and hardware optimization, our tutorial aims to enable 
developers from a larger set of backgrounds to start tapping into the 
potential of FPGAs with real high performance codes.

This tutorial will cover modeling, designing and implementing FPGA 
hardware using a modern HLS tool. We include aspects of performance 
modeling, but the majority of the tutorial will focus on practice, with 
the goal of enabling attendees to start writing parallel hardware of 
their own.
We use code examples to introduce central properties of the mapping from 
imperative languages to hardware, and the performance aspects implied by 
this transformation. Examples will be demonstrated with short to medium 
length live coding sessions interleaved with the presentation.

The material covered in the demos will be handed out to attendees prior 
to the tutorial, in additional to a virtual machine with the tools 
necessary to run the examples.

We hope to see you at SC!

Best regards,
Johannes de Fine Licht, Torsten Hoefler

### qreharg rug ebs fv crryF --- http://htor.inf.ethz.ch/ ---
Torsten Hoefler           | Associate Professor
Dept. of Computer Science | ETH Zürich
Universitätsstrasse 6     | Zurich-8092, Switzerland
CAB F 75                  | Phone: +41 44 632 68 79

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