[hpc-announce] AISTECS 2018 - Call for Papers (Interconnects, Multiprocessors)

[Sergi Abadal]

Dear researcher,

In case you would be interested, we let you know that the deadline for the
AISTECS workshop has been extended to December 2nd. We are looking forward
to your submissions.

More info below and in the attached pdf version.

Kind regards,
Sergi

*** Apologies if you receive multiple copies of this call for papers ***

http://mpsoc.unife.it/~aistecs/index.html

The AISTECS workshop is the 4th edition of successfully blending the
INA-OCMC workshop (9 editions at HiPEAC) and the envelope-pushing Silicon
Photonics workshop (2 editions at HiPEAC) into one. The AISTECS workshop
promotes research and knowledge exchange on advanced interconnect designs
leveraging emerging technologies to support a wide variety of computing
platforms ranging from high-performance computing systems and datacenters
down to embedded and Internet of Things (IoT) devices. The workshop aims to
gather a complete range of perspectives, spanning from raw technology
issues and solutions up to studies at the overall system level of modern
multi-/many-core systems. This encompasses novel network solutions from
both academic and industrial researchers.


*Important Dates*

   - *Submission deadline (extended)*: December 2nd, 2018 (11h59p AoE –
   anywhere on earth)
   - *Author notification:* December 8th, 2018
   - *Camera-ready paper due:* December 22nd, 2018


*Submission Format and Website*

AISTECS welcomes both short work-in-progress articles describing breaking
new ideas, as well as full papers with more mature evaluations. All papers
will undergo a single-blind peer review process, emphasizing
novelty/potential in the work-in-progress submissions and
implementation/evaluation in the full paper submissions. Presentation times
will be allocated according to the type of paper. Work-in-progress papers
are limited to 2 pages, whereas full papers are limited to 4 pages (A4).
All articles must be formatted in accordance to the ACM two-column style (
https://www.acm.org/publications/proceedings-template), including title,
authors, affiliations and corresponding author email. Papers deviating
significantly from the paper size and formatting rules may be rejected
without review.

Papers must be submitted in PDF format via EasyChair
https://easychair.org/conferences/?conf=aistecs2019

Accepted papers will be published in the ACM Digital Library within the ACM
International Conference Proceedings Series (ICPS). Authors will be sent
the ACM form and instructions to finalize the camera-ready submission and
to complete the publication procedure (To be confirmed).


*Workshop Topics*

   - *Emerging Interconnect Technologies* (Silicon photonics, wireless, and
   RF / Carbon nanotubes, through-silicon vias, near-field coupling
   interconnects / NoCs for 3D and 2.5D packages, including interposer-based
   systems)
   - *Reliability and Security* (Reliability, availability, fault tolerance
   for system communication / Fault-tolerant routing, approximate NoCs /
   Secure intra-chip and inter-chip communication, mitigation of hardware
   trojan effects)
   - *Performance, Power, Energy and Thermal Issues* (Benchmarks,
   simulation, performance and Quality of Service (QoS) management /
   Thermal-/energy-and power-related NoC optimization and dark silicon /
   Thermal-aware designs in silicon photonics and 3D NoCs / Impact of the
   interconnect on application performance / Network solutions for performance
   isolation in many-cores)
   - *NoC Architecture and Implementation* (Topologies, routing, flow
   control / Synchronous/asynchronous interconnects / Design methodologies and
   tools / Signaling & circuit design for NoC links)
   - *Interconnect Design for Memory Subsystems* (Memory interconnect and
   coherence support / NoC support for memory and cache access / Programming
   models for shared memory, message passing and novel programming models)
   - *Internet of Things, High Performance Computing and GPUs* (Interconnect
   solutions for heterogeneous GPU/FPGA-based multi/macro-chip systems /
   Communication infrastructures for HPC systems, Supercomputers and Data
   Centers / Reconfigurable/programmable interconnect components /
   Interconnect architectures for neuromorphic computing / Network
   infrastructures for Internet-of-Things devices)
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