[hpc-announce] CFP: CHAMLA-2019 -- First Workshop on Co-Design of Hardware Acceleration for Machine Learning Algorithms

[Håkan Grahn]

###########################################################################
#
#    Call for Papers
#
#    First Workshop on Co-Design of Hardware Acceleration
#    for Machine Learning Algorithms (CHAMLA-2019)
#
#    January 21, 2019, Valencia, Spain (Co-located with HiPEAC 2019)
#    http://chamla2019.cse.bth.se
#
###########################################################################

Scope of the workshop

Nowadays AI scientist and engineers are interested in proposing new models by
rapid-prototyping new algorithms and methods in highly abstracted frameworks
like TensorFlow, PyTorch etc. Such frameworks, apart from ‘hiding’ most of the
underlying computations and learnt parameters from the user, they also offer
automated optimization methods for the training of the designed algorithm.

On the other hand, HW scientists and engineers try to offer alternative
solutions in accelerating machine learning tasks beyond GPUs using heterogeneous
hardware like FPGAs. Since their tools are working in a completely different
abstraction level from those broadly used by the AI community, accelerating
ML algorithms in custom hardware is an extremely difficult and laborious task.
What would be a solution to this? There is a need for a tighter collaboration
between the two fields and thus the best solutions will emerge from the
co-design of the hardware and algorithms.

Since the most highly abstracted tools for FGPA development are working only
at a subset of C/C++ (HLS), an efficient methodology should be developed in
order to bridge the gap between the modeling in modern AI frameworks and the
deployment in FPGAs using low level HLS frameworks.

The proposed workshop will address design strategies aiming at a fast and
efficient deployment of machine learning methods in accelerated hardware.
Starting from the problem and by taking into consideration various aspects,
the workshop will cover state-of-the-art methodologies and techniques to
enable an efficient design workflow.

Topics

* Embedded (parallel) Computer Architectures: embedded homogeneous and
  heterogeneous multicore architectures, embedded reconfigurable architectures,
  embedded real-time systems, mixed criticality system support, dependable
  systems.
* High-Performance Computer Systems: parallel homogeneous and/or heterogeneous
  multi- and many-core systems
* Strict constrained systems: Extreme low-power/energy consumption, low latency
  for fast/real- time response, low memory capacity
* Efficient ML and DL Algorithms for Training and Inference
* Approximate computing techniques applied to ML/DL

Submission of papers / abstracts

We are particularly looking for contributions from early-stage research projects
and preliminary results. The objective of the workshop is to trigger a discussion
in the community on an emerging and important topic.

Submission is open for position papers / extended abstracts up to two pages in
ACM two-column format, \url{https://www.acm.org/publications/proceedings-template}.
Submissions should be done in pdf-format on \url{https://easychair.org/conferences/?conf=chamla2019}.
Submissions will be evaluated on the basis of technical quality, novelty,
potential impact, and clarity.

Authors of accepted abstracts will be invited to present their work at the
workshop, and accepted abstracts will be published on the workshop web site.
No copyright transfer is done, thus it should not prohibit further publication.

Important dates

December 7: Submission
December 14: Notification
December 25: Early registration
January 14: Camera ready
January 21: Workshop

Organizers

Antonios Nikitakis, Synelixis Solutions, Greece, ikitakis at synelixis.com<mailto:nikitakis at synelixis.com>
Håkan Grahn, Blekinge Institute of Technology, Sweden, Hakan.Grahn at bth.se<mailto:Hakan.Grahn at bth.se>
Pedro Trancoso, Chalmers University of Technology, Sweden, ppedro at chalmers.se<mailto:ppedro at chalmers.se>

Location

The workshop will be co-located with HiPEAC-2019 in Valencia, Spain,
https://www.hipeac.net/2019/valencia/

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