[hpc-announce] Call for Papers - Journal Special Issue JPDC on Advanced Interconnection Network Architectures for Supercomputers and Data-Centers (HiPINEB 2018)
Jesús Escudero Sahuquillo
Jesus.Escudero at uclm.es
Sun Mar 4 05:55:21 CST 2018
[Apologies if you received multiple copies of this CFP]
Special Issue on Advanced Interconnection Network Architectures for
Supercomputers and Data-Centers (HiPINEB 2018)
Journal of Parallel and Distributed Computing
* Pedro Javier Garcia, University of Castilla-La Mancha, Spain
* Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain
By the year 2023, High-Performance Computing (HPC) Systems are expected
to break the performance barrier of the Exaflop (10^18 FLOPS) while
their power consumption is kept at current levels (or increases
marginally), what is known as the Exascale challenge. In addition, more
storage capacity and data-access speed is demanded to HPC clusters and
datacenters to manage and store huge amounts of data produced by
software applications, what is known as the Big-Data challenge. Indeed,
both the Exascale and Big-Data challenges are driving the technological
revolution of this decade,
motivating enormous research and development efforts from industry and
academia. In this context, the interconnection network plays an
essential role in the architecture of HPC systems and datacenters, as
the number of processing or storage nodes to be interconnected in these
systems is very likely to grow significantly to meet the higher
computing and storage demands. Besides, the capacity of the network
links is expected to grow, as the roadmaps of several interconnect
technologies forecast. Therefore, the interconnection network should
provide a high communication bandwidth and low latency, otherwise the
network would become the bottleneck of the entire system. In that
regard, many design aspects are considered for improving the
interconnection network performance, such as topology, routing
algorithm, power consumption, reliability and fault tolerance,
congestion control, programming models, control software, etc. In this
Special Issue we will gather high-quality papers from both the community
and those presented in the workshop HiPINEB 2018. The topics covered in
this Special Issue are related with the above design aspects, and also
we look for research papers in emerging ideas and technologies for
high-speed and low-latency interconnect architectures, communication
protocols, traffic characterization and simulation tools.
Best papers among those selected for HiPINEB 2018 will be invited to
submit a paper to a Journal Special Issue on the Elsevier's Journal of
Parallel and Distributed Computing (JPDC) with impact factor: 1.930 (JCR
2016). In addition, we also encourage to submit a paper to this special
issue to all researchers and professionals, both from industry and
academia, working in the area of interconnection networks for scalable
HPC systems and Datacenters, and especially those involved in Exascale
performance and Big-Data.
TOPICS OF INTEREST
The list of topics covered by this Special Issue includes, but is not
limited to, the
* Interconnect architectures and network technologies for high-speed,
* Scalable network topologies, suitable for interconnecting a huge
number of nodes.
* Power saving policies in the interconnect devices and network
infrastructure, both at software and hardware level.
* Emerging ideas, work-in-progress and early, high-impact achievements.
* Good practices in the configuration of the network control software.
* Network communication protocols: MPI, RDMA, Hadoop, etc.
* APIs and support for programming models.
* Routing algorithms.
* Quality of Service (QoS).
* Reliability and Fault tolerance.
* Load balancing and traffic scheduling.
* Network Virtualization.
* Congestion Management.
* Applications and Traffic characterization.
* Modeling and simulation tools.
* Performance Evaluation.
Note, however, that papers focused on topics that are too far from the
design, development and configuration of high-performance interconnects
for HPC systems and Datacenters (e.g., mobile networks, intrusion
detection, peer-to-peer networks or grid/cloud computing) will be
automatically considered as out of scope and rejected without review.
* First submission date: March 1, 2018
* Submission Deadline: May 30, 2018
* Acceptance deadline: December 30, 2018
* Estimated publication date: April 1, 2019 (tentative)
INSTRUCTIONS FOR AUTHORS
This is an open call for contributions, but also invites extended
selected papers from the 4rd IEEE Workshop on High-Performance
Interconnection Networks in the Exascale and Big-Data Era (HiPINEB 2018).
* Extended versions of conference papers must contain at least 50% new
* To submit a paper you must go to this website:
https://ees.elsevier.com/jpdc and login with your credentials. In the
"Choose Article Type" Box, you must choose the option "VSI: AINA"
* Each manuscript should be accompanied by a cover letter outlining the
basic findings of the paper
and their significance.
* Manuscripts should be no longer than 35 double-spaced pages, not
including the title page, abstract,
or references. Number all pages consecutively and organize the paper as
- Title page (page 1). This page should contain the article title,
authors' names and complete affiliations, footnotes to the title, and
the address for manuscript correspondence (including e-mail address and
telephone and fax numbers).
- Abstract (page 2). The abstract must be a single paragraph that
summarizes the main findings of the paper in less than 150 words.
- After the abstract a list of up to 10 keywords that will be
useful for indexing or searching should be included.
Authors must read the guide for authors in the following link:
For more information about this special issue or if you have any
question, please contact
the guest editors at jesus.escudero at uclm.es or pedrojavier.garcia at uclm.es
Logotipo UCLM <http://www.uclm.es>
Escuela Superior de Ingeniería Informática <http://www.esiiab.uclm.es/>
*Jesus Escudero Sahuquillo
* Investigador acceso al SECTI
*Universidad de Castilla-La Mancha*
Departamento de Sistemas Informáticos <http://www.albacete.org> (DSI)
Instituto de Investigación en Informática de Albacete
Escuela Superior de Ingeniería Informática <https://www.esiiab.uclm.es/>
Campus Univ. s/n, 02071 - Albacete
Tfno: 967 599 200 <tel:+34:967599200> | Ext: 2661 <tel:+34:2661> |
jesus.escudero at uclm.es <mailto:jesus.escudero at uclm.es>
Página Personal <http://hipineb.i3a.info/jescudero/> | Mensaje
Instantáneo <sip:jesus.escudero at uclm.es>
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