[hpc-announce] Call for papers: The 14th International Workshop on High-Performance, Power Aware Computing (HPPAC'18) Extended deadline to February 2nd, 2018

[Manzano, Joseph B]

    The 14th International Workshop on High-Performance, Power Aware Computing (HPPAC'18)
                                  https://sites.google.com/site/hppac18/

Program co-chairs:     Shuaiwen Leon Song, Pacific Northwest National Lab and College of William & Mary
                                           Natalie Bates, Energy Efficient HPC Working Group
                                           Ang Li, Pacific Northwest National Lab

Publicity Chair:             Joseph Manzano, Pacific Northwest National Lab

Venue
-----

To be held on Monday, May 21st, in conjunction with the 32nd IEEE International Parallel and Distributed Processing Symposium (IPDPS 2018)

Overview
--------

Power and energy are now recognized as first-order constraints in high-performance computing. Optimizing performance  under power and energy bounds requires coordination across not only the software stack (compilers, operating and runtime systems, job schedulers) but also coordination with cooling systems and outwards to electrical suppliers. As we continue to move towards exascale and extreme scale computing, understanding how power translates to performance becomes an increasingly critical problem.

The purpose of this workshop is to provide a forum where cutting-edge research in the above topic can be shared with others in the community. We welcome submissions addressing power aware computing issues. All papers will be subject to single-blind peer review, and the quality of standard papers is expected to be high.

Topics of particular interest include (but are not limited to):

* Performance optimization under node, job, cluster and site power bounds
* Power/performance tradeoffs across accelerators, processors and DRAM
* Cooling/performance tradeoffs
* Translating budgetary bounds into power and energy bounds.
* Power-efficient system design, from computer center to silicon
* Effects of compiler optimizations on application power and energy efficiency
* Power- and energy-aware job schedulers, runtime systems and operating systems
* Models of power and performance, from processors and components to computer centers
* Evaluations of hardware power and energy controls
* Applications specific power and energy optimization

Submission Guidelines
---------------------

Papers should not exceed ten single-spaced pages for long papers (including figures, tables and references) or four single-spaced pages for short papers (not including the references) using 12-point font on 8.5x11- inch pages.
Submissions will be judged on correctness, originality, technical strength, significance, presentation quality, and relevance. Submitted papers should not have appeared in or be under consideration for another venue. A full peer-review process will be followed with each paper being reviewed by at least three members of the program committee.

Submissions should follow the IEEE Conference Proceedings templates found at http://www.ieee.org/conferences_events/conferences/publishing/templates.html . Camera-ready copy will need to conform to IPDPS guidelines; these will be announced during author notification.

Important dates
---------------

Paper Submission (for both short and long papers):   Extended to February 2nd, 2018
Paper Notification:                               February 28th, 2018
Final Paper Due:                                     March 7th, 2018
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.mcs.anl.gov/mailman/private/hpc-announce/attachments/20180108/daa0811b/attachment-0001.html>