[hpc-announce] Deadline Extension for Call for Papers (Sep 09 AOE) - MCHPC'18 at SC18: Workshop on Memory Centric High Performance Computing

Yonghong Yan yanyh15 at gmail.com
Tue Aug 28 08:46:30 CDT 2018

Call for Papers

*MCHPC'18: Workshop on Memory Centric High Performance Computing*
                 held in conjunction with SC18: The International
Conference on High Performance Computing, Networking, Storage and Analysis

Location: Kay Bailey Hutchison Convention Center, Dallas, TX USA
Time/Date: 9:00AM - 5:30PM, Sunday, November 11, 2018


Submission Deadline: September 9 2018 AOE


The growing disparity between CPU speed and memory speed, known as the
memory wall problem, has been one of the most critical and long-standing
challenges in the computing industry. The situation is further complicated
by the recent expansion of the memory hierarchy, which is becoming deeper
and more diversified with the adoption of new memory technologies and
architectures including 3D-stacked memory, non-volatile random-access
memory (NVRAM), memristor, hybrid software and hardware caches, etc.
Computer architecture and hardware system, operating systems, storage and
file systems, programming stack, performance model and tools are being
enhanced, augmented, or even redesigned to address the performance,
programmability and energy efficiency challenges of the increasingly
complex and heterogeneous memory systems for HPC and data-intensive

The MCHPC workshop aims to bring together computer and computational
science researchers, from industry, government labs and academia, concerned
with the challenges of efficiently using existing and emerging memory
systems for high performance computing. The term performance for memory
system is general, which include latency, bandwidth, power consumption and
reliability from the aspect of hardware memory technologies to what it is
manifested in the application performance. The topics of interest for the
MCHPC workshop include, but are not limited to:

   - The challenges and software and hardware solutions of using 3-D stack
   memory, NVDIMM, memristor and other processor/compute-in-memory technology.
   - Programing interfaces or language extensions that improve the
   programmability of using emerging memory technologies and systems.
   - Compiler and runtime techniques for optimizing data layout, movement
   and consistency enforcement for latency hiding and for improving bandwidth
   utilization and energy consumption of memory systems.
   - Enhancement or new development for operating systems, storage and file
   systems, and I/O system that address existing and emerging memory systems.
   - Modeling, evaluation, and case study of memory system behavior and
   application performance that reveal the limitation and characteristics of
   existing memory systems.
   - Application development and optimization for memory architecture and

*Important Dates*

   -  Submission Deadline -- Sep 9 2018 AoE
   -  Notifications -- September 21 2018
   -  Camera Ready Papers or Submission of Extended Journal Version -- TBD
   -  November 11th 2018 - MCHPC2018 Workshop


   - Yonghong Yan (University of South Carolina, yanyh at cse.sc.edu)
   - Ron Brightwell (Sandia National Laboratory, rbbrigh at sandia.gov)
   - Xian-He Sun (Illinois Institute of Technology, sun at iit.edu)
   - Maya B Gokhale (Lawrence Livermore National Laboratory,
   gokhale2 at llnl.gov)

*Program Committee*

   - Ron Brightwell (Co-Chair, Sandia National Laboratory,
   rbbrigh at sandia.gov)
   - Yonghong Yan (Co-Chair, University of South Carolina, yanyh at cse.sc.edu)
   - Xian-He Sun (Illinois Institute of Technology)
   - Maya B Gokhale (Lawrence Livermore National Laboratory)
   - Mingyu Chen (Chinese Academy of Sciences)
   - Bronis R. de Supinski (Lawrence Livermore National Laboratory)
   - Tom Deakin (University of Bristol)
   - Wendy Elasser (Arm Ltd)
   - Hal Finkel (Argonne National Laboratory and LLVM Foundation)
   - Kyle Hale (Illinois Institute of Technology)
   - Jeff R. Hammond (Intel Corporation)
   - Dong Li (University of California, Merced)
   - Scott Lloyd (Lawrence Livermore National Laboratory)
   - Ivy B. Peng (Oak Ridge National Laboratory)
   - Christian Terboven (RWTH Aachen University)
   - Alice Koniges (Univ. of Hawaii, Maui High Performance Computing Center)


Authors are invited to submit manuscripts in English structured as
technical papers up to 8 pages or as short papers up to 5 pages, both of
letter size (8.5in x 11in) and including figures, tables, and references.
Submissions not conforming to these guidelines may be returned without
review. Your paper should be formatted using sigconf of the ACM Master
Article Template from https://www.acm.org/publications/proceedings-template

All manuscripts will be reviewed and judged on correctness, originality,
technical strength, and significance, quality of presentation, and interest
and relevance to the workshop attendees. Submitted papers must represent
original unpublished research that is not currently under review for any
other conference or journal. Papers not following these guidelines will be
rejected without review and further action may be taken, including (but not
limited to) notifications sent to the heads of the institutions of the
authors and sponsors of the conference. Submissions received after the due
date, exceeding length limit, or not appropriately structured may also not
be considered. At least one author of an accepted paper must register for
and attend the workshop. Authors may contact the workshop organizers for
more information.

Papers should be submitted electronically at:
https://submissions.supercomputing.org/ using the "SC18 Workshop: MCHPC18"

We are working on proceeding details and the tentative plan is to invite
papers presented at the workshop for an expanded version for consideration
in a journal special issue.
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