[hpc-announce] [MICRO] Last week for early registration deadline - The 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

[Ramon Bertran]

**MICRO-50 - Early registration deadline - Call For Participation**

Important dates
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Early registration deadline Sep 15th, 2017, 11:59p.m. (US EST)
Registration deadline        Oct 13th, 2017, 11:59p.m. (US EST)
Conference: Oct 14-18th, Boston, Massachusetts, US

Important links
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Registration: https://whova.com/portal/registration/aiism_201710/
Hotel Reservation: https://aws.passkey.com/go/Micro50Conference2017
Visa: https://www.microarch.org/micro50/Visa/
Student Travel grant: https://www.microarch.org/micro50/StudentTravel/ 

Stay informed
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Download Phone App: https://whova.com/portal/aiism_201710
Webpage: https://www.microarch.org/micro50/
News: Twitter @MicroArchConf Hashtag: #MICRO50

Conference information
----------------------

The International Symposium on Microarchitecture (MICRO) is
the premier forum for the presentation and discussion of new
ideas in microarchitecture, compilers, hardware/software
interfaces, and design of advanced computing and communication
systems. The goal of MICRO is to bring together researchers
in the fields of microarchitecture, compilers, and systems
for technical exchange. The MICRO community has enjoyed
having close interaction between academic researchers and
industrial designers---we aim to continue and strengthen
this longstanding tradition at the 50th MICRO in
Boston, Massachusetts.

The main conference program will cover the following topics:

* Processor, memory, interconnect, and storage architectures.
* Hardware, software, and hybrid techniques for improving
  system performance, energy-efficiency, cost, complexity,
  predictability, quality of service, reliability,
  dependability, security, scalability, programmer
  productivity, etc.
* Architectures for instruction-level, thread-level,
  and memory-level parallelism: superscalar, VLIW,
  data-parallel, multithreaded, multicore, manycore, etc.
* Compiler and microarchitectural techniques for
  parallelism (ILP, TLP, MLP).
* Low-power, high-performance, and cost/complexity-efficient
  architectures.
* Architectures for emerging platforms, including
  smartphones, cloud/datacenter, etc.
* Architectures and compilers for embedded processors,
  DSPs, GPUs, ASIPs (network processors, multimedia,
  wireless, deep learning, neuromorphic, etc.).
* Advanced software/hardware speculation and prediction schemes.
* Microarchitecture techniques to better support system
  software, programming languages, programmability, and compilation.
* Microarchitecture modeling and simulation methodology.
* Insightful experimental and comparative evaluation and
  analysis of existing microarchitectures, hardware/software
  mechanisms and workloads.

In addition, the following workshops and tutorials will take place:

* Workshops:
  * Exploiting Accelerator Diversity for Cognitive Workloads
  * Workshop on Network on Chip Architectures (NoCArc)
  * Career Workshop for Women and Minorities in Computer Architecture
  * First Workshop on RISC-V for Computer Architecture Research (CARRV)
  * Cognitive Edge Computing
  * Workshop On Negative Outcomes, Post-mortems, and Experiences
* Tutorials:
  * Tutorial on Hardware Architectures for Deep Neural Networks
  * Tutorial on Microarchitecture Level Reliability Assessment:
    Throughput and Accuracy
  * An Introduction to OpenPiton, a Manycore Open Source Processor