[hpc-announce] 2017 E2SC Call for Papers DEADLINE Extension to September 15, 2017

Manzano, Joseph B Joseph.Manzano at pnnl.gov
Thu Sep 7 11:09:40 CDT 2017

                        5th International Workshop on
                    Energy Efficient SuperComputing (E2SC)
                                       November 13rd, 2017
               Held in conjunction with SC'17, Denver, Colorado, USA
                          November 12th-17th, 2017
                                                In cooperation with SIGHPC
                                Call for Papers


With Exascale systems on the horizon, we will be ushering in an era with power
and energy consumption as a key concern for scalable computing.
To achieve viable high performance, a combination of evolutionary
and revolutionary methods is required with a stronger integration
among hardware features, system software and applications.
Equally important are the capabilities for fine-grained spatial and temporal
measurement and control to facilitate energy efficient computing across
all layers. Current approaches for energy efficient computing rely heavily on
power efficient hardware in isolation. However, it is pivotal for hardware to
expose mechanisms for energy efficiency to optimize power and energy
consumption for various workloads and to reduce data motion, a major component
of energy use. At the same time, high fidelity measurement techniques,
typically ignored in data-center level measurement, are of high importance
for scalable and energy efficient inter-play at different layers of
application, system software and hardware.

This workshop seeks to address the important energy efficiency aspects in the
HPC community that have not been previously addressed by aspects covered in
the data center or cloud computing communities. Emphasis is given to an
application's view related to significant energy efficiency improvements
as well as to the required hardware/software stack that must include
necessary power and performance measurement, and analysis harnesses.

Current tools are often limited by hardware capabilities and their lack of
information about the characteristics of a given workload/application. In the
same manner, hardware techniques, like dynamic voltage frequency scaling, are
often limited by their granularity (very coarse power management) or by their
scope (a very limited system view). More rapid realization of energy savings
will require significant increases in measurement resolution and optimization
techniques.  Moreover, the interplay between performance, power and
reliability add another layer of complexity to this already difficult group
of challenges.

Workshop Focus

We encourage submissions in the following areas:

- Tools for power and energy analysis with different granularities and
  scope from hardware (e.g., component, core, node, rack, system) or
  software views (e.g., threads, tasks, processes, etc.) or both.
- Tools and techniques for measurement, analysis, and modeling of thermal
  effects at different granularities (e.g., component, core, node, rack,
  system) for large-scale systems.
- Techniques that enable power and energy optimizations at different
  scale levels for HPC systems.
- Integration of power-aware technologies in applications and throughout
  the software stack of HPC systems.
- Characterization of current state-of-the-art HPC systems and
  applications in terms of power.
- Disruptive infrastructure hardware technologies for energy-efficient
- Analysis of future technologies that will provide improved energy
  consumption and management on future HPC systems.

Organizing Committee

General Chairs: Kirk Cameron, Virginia Tech, USA
                Adolfy Hoisie, PNNL, USA
                David Lowenthal, University of Arizona, USA
                Dimitrios S. Nikolopoulos,Queen's University of Belfast,UK
                Sudha Yalamanchili, Georgia Institute of Technology, USA

Program Co-Chairs:  Jim Larus, Sandia, SNL, USA
                    Kevin J. Barker, PNNL, USA

Publicity Chair:   Andres Marquez, PNNL, USA
European Liaison:  Michele Weiland, EPCC, UK

Publication Chair:  Joseph Manzano, PNNL, USA

Panel Chair:  Barbara Chapman, SUNY/BNL, USA

Important Dates

Paper Submission            15th September 2017
Paper Notification           27th September 2017
Final Papers Due              4th October 2017

Submission Guidelines

Papers should not exceed eight (for long format) or four (for short format)
single-space pages (including figures, tables and references) using a 10-point
on 8.5x11-inch pages (US Letter).

Submissions will be judged on correctness, originality, technical strength,
significance, presentation quality and appropriateness.
Submitted papers should not have appeared in or
should not be under consideration for another venue.
A full peer-review processes will be followed with each paper being reviewed
by at least 3 members of the program committee.
Submissions will be made through EasyChair https://easychair.org/conferences/?conf=e2sc0

Technical Program Committee

* Natalie Bates, Energy Efficient HPC Working Group, USA
* Laura Carrington, San Diego Super Computing Center, USA
* Vladimir Getov, University of Westminster, UK
* Roberto Gioiosa, Pacific Northwest National Laboratory, USA
* Eric Van Hensbergen, ARM Research, USA
* Lennart Johnsson, University of Houston, USA
* Hyesoon Kim, Georgia Tech, USA
* Dong Li, University of California Merced, USA
* Aniruddha Marathe, Lawrence Livermore National Laboratory, USA
* Benoit Meister, Reservoir Labs, USA
* Barry Rountree, Lawrence Livermore National Laboratory, USA
* Sameer Shende, University of Oregon, USA
* Shuaiwen Leon Song, Pacific Northwest National Laboratory, USA
* Nick Wright, Lawrence Berkeley National Laboratory, USA
* Rengan Xu, Dell Inc, USA
* Andrew Younge, Sandia National Laboratory, USA
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