[hpc-announce] CFP: Special Issue of CC-PE on Processors, Interconnects, Storage and Caches for Exascale Systems (Extended deadline)

Manuel E. Acacio Sánchez meacacio at um.es
Fri Nov 24 02:35:04 CST 2017

Concurrency and Computation: Practice and Experience (CC-PE) journal 
will publish a special issue dedicated to "Processors, Interconnects, 
Storage and Caches for Exascale Systems". Please submit your 
contribution to Manuscript Central 
(https://mc.manuscriptcentral.com/cpe) as "PISCES2017" special issue


Exascale computing constitutes nowadays a significant challenge. 
Although traditional computer systems continue to making important 
advances, reaching exascale requires mass customization. With this aim, 
several ongoing research projects are focusing on different 
architectural (computing boards or nodes, interconnects, storage, etc) 
issues of future exascale systems. Most of them devise heterogeneous 
computing boards consisting of CPUs (high performance and/or low power), 
FPGAs, GPUs, accelerators, etc sharing a common memory hierarchy. In 
this context, efficient intra-, inter-board within the same rack and 
inter-rack interconnects with the memory hierarchies are required. Also, 
performance and reliability design constraints for exascale storage 
systems are significant challenges for HPC system designers. High 
performance I/O is an important aspect, because storing and retrieving 
such large amounts of data can greatly affect the overall performance of 
applications. Finally, it is important to characterize the demands that 
exascale applications exert on the different components of an exascale 
system. This special issue seeks to provide an opportunity for the 
researchers to present their original contributions on novel ways of 
tackling all these aspects of future HPC systems.


- Heterogeneous node designs: CPU, GPUs/Accelerators and FPGAs.
- On-chip and off-chip cache designs.
- Interconnects for Exascale: electrical and optical networks.
- Cache coherence in Exascale Computing.
- Coherent DRAM-based cache designs.
- Storage in Exascale systems.
- Power saving policies at different hardware levels.
- Hardware prototyping (FPGA hardware implementation and timing and 
energy characterization).
- Applications characterization (bandwidth requirement, traffic, 
scalability, …) for exascale computing.


- Submit at CCPE Home Page - Concurrency and Computation: Practice and 
Experience as "PISCES2017" special issue.
- Submissions should be be prepared for publication according to the 
journal submission guidelines
- The submitted papers must have at least 50% difference from any other 
published paper.
- Papers should not exceed 16 pages in length.


- Submission deadline: January 1, 2018 (extended)
- First round review results: February 1, 2018
- Submission deadline for revised versions of the manuscripts: March 1, 
- Final decision: May 1, 2018
- Electronic Publication: four months after all final papers submitted.


Julio Sahuquillo, Universitat Politècnica de Valencia, Spain 
(jsahuqui at disca.upv.es).
Manuel E. Acacio, Universidad de Murcia, Spain (meacacio at um.es).


Dr. Manuel Eugenio Acacio Sánchez
Dept. Ingeniería y Tecnología de Computadores
Universidad de Murcia
Campus Espinardo, Facultad de Informática
30100 Murcia - SPAIN
Phone: +34 868 883983    Fax: +34 868 884151
e-mail:meacacio at ditec.um.es

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