[hpc-announce] CFP: RePara 2017 Workshop. Reengineering for Parallelism.

[JOSE DANIEL GARCIA SANCHEZ]

[Apologies if you got multiple copies of this email]
________________________________________________________________________

*The 3rd International Workshop on Reengineering for Parallelism in
Heterogeneous Parallel Platforms (REPARA 2017)*
https://www.arcos.inf.uc3m.es/repara2017/

Held in conjunction with the International Conference of Parallel Computing
(ParCo 2017)
http://www.hpc.cineca.it/content/parco-2017

Bologna, Italy
September, 12-15, 2017

ATTENTION: New Dates
===================================
Submission deadline: June, 30, 2017
Notifications: July, 28, 2017

Abstract
===================================

In recent years, traditional processors have not been able to directly
translate chip fabrication technology advances intro performance gains. To
keep satisfying the demand for computing power, there is a shift from
homogeneous machines to heterogeneous architectures combining different
kinds of processors (CPUs, GPUs, DSPs, FPGAs, and other accelerators).
While this approach has allowed significant performance and energy
efficiency benefits, heterogeneous systems are often highly difficult to
program with existing tools. To reduce the cost of system development,
reengineering techniques emerge as a solution which may help to balance
ease-of-development with better performance, better reliability, and lower
maintenance costs.

The RePara2017 workshop it aims to join experts from related disciplines to
share recent advances in different areas contributing to better
transformation of new and legacy applications to different programming
models for diverse computing devices in the context of parallel
heterogeneous architectures.

Scope and Interest
===================================

Topics of interest include, but are not limited to:

+ High-level parallel programming models, libraries and languages for
Heterogeneous Parallel Platforms.
+ Compiler support for Heterogeneous Parallel Systems.
+ Description languages for Heterogeneous Parallel Platforms.
+ Parallel patterns for Heterogeneous Platforms.
+ Autonomic management of Power/Performance trade-offs.
+ Automated kernel identification and assessment.
+ Software refactoring approaches for parallel programming models.
+ Transformations from source code to reconfigurable hardware.
+ Integration of FPGA accelerators into refactored software.
+ Runtimes for software coordination and task mapping in Heterogeneous
Parallel Platforms.
+ Scheduling for Heterogeneous Parallel Platforms.
+ Performance modeling and prediction in Heterogeneous Parallel Platforms.
+ Energy efficiency monitoring and prediction in Heterogeneous Parallel
Platforms.
+ Software quality assessment in parallel programming models with special
attention to maintainability.
+ Applying partitioning and mapping for parallel Heterogeneous computing
architectures.
+ Application experiences of refactoring to software in industrial domains.


Workshop publication
===================================

Accepted paper will be published in the proceedings of the ParCo 2017
Conference.

Authors of accepted papers, or at least one of them, are requested to
register and present their work at the conference. Authors of accepted
papers, or at least one of them, are requested to register and present
their work at the conference, otherwise their papers will be removed from
the proceedings book prior to its publication.

Journal Publication
===================================

Extended version of selected papers from the workshop will be invited by
the RePara2017 program committee for publication, after further revision,
in an special issue of an International Journal (to be announced).


Submission Instructions
===================================

Papers submitted to the workshop should be written in English conforming to
the IOS Press Book format (see templates at IOS Press site at
http://www.iospress.nl/service/authors/latex-and-word-
tools-for-book-authors/). The paper should be submitted through the
workshop submission system at EasyChair (https://easychair.org/confere
nces/?conf=repara2017). The length of the papers should not exceed 10 pages.


Contact
===================================

Please email inquiries concerning the workshop to J. Daniel Garcia (
josedaniel.garcia at uc3m.es).
-- 
Prof. J. Daniel Garcia
Associate Professor - Profesor Titular de Universidad
Computer Architecture Group
University Carlos III of Madrid
Avenida de la Universidad, 30
28911 Leganés, Madrid. Spain
Tel: +34 91 624 6044
Fax: +34 91 624 9129
e-mail: josedaniel.garcia at uc3m.es
Web: http://www.arcos.inf.uc3m.es/~jdaniel

Linked-In: http://es.linkedin.com/in/jdanielgarcia
Twitter: http://www.twitter.com/jdgarciauc3m


-- 
Prof. J. Daniel Garcia
Associate Professor - Profesor Titular de Universidad
Computer Architecture Group
University Carlos III of Madrid
Avenida de la Universidad, 30
28911 Leganés, Madrid. Spain
Tel: +34 91 624 6044
Fax: +34 91 624 9129
e-mail: josedaniel.garcia at uc3m.es
Web: http://www.arcos.inf.uc3m.es/~jdaniel

Linked-In: http://es.linkedin.com/in/jdanielgarcia
Twitter: http://www.twitter.com/jdgarciauc3m


-- 
Prof. J. Daniel Garcia
Associate Professor - Profesor Titular de Universidad
Computer Architecture Group
University Carlos III of Madrid
Avenida de la Universidad, 30
28911 Leganés, Madrid. Spain
Tel: +34 91 624 6044
Fax: +34 91 624 9129
e-mail: josedaniel.garcia at uc3m.es
Web: http://www.arcos.inf.uc3m.es/~jdaniel

Linked-In: http://es.linkedin.com/in/jdanielgarcia
Twitter: http://www.twitter.com/jdgarciauc3m
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