[hpc-announce] PISCES 2017 - Final CFP: Deadline Extended to May 12

[Manuel E. Acacio Sánchez]

[Apologies if you got multiple copies of this email]

************************** CALL FOR PAPERS ****************************

First International Workshop on Processors, Interconnects, Storage and
Caches for Exascale Systems (PISCES 2017)  http://pisces2017.github.io

As part of 23rd Intl. European Conference on Parallel and Distributed
Computing (Euro-Par 2017)  http://europar2017.usc.es/

August 29, 2017
Santiago de Compostela, Spain

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Submission Deadline (extended): *May 12, 2017*


SCOPE AND OBJECTIVES

Exascale computing constitutes nowadays a significant challenge.
Although traditional computer systems continue to making important
advances, reaching exascale requires mass customization. With this aim,
several ongoing European Projects are focusing on different
architectural aspects of exascale systems. Most of these projects focus
on heterogeneous computing boards consisting of CPUs (high performance
and/or low power), FPGAs, GPUs, accelerators, etc sharing a common
memory hierarchy. In this context, efficient intra-, inter-board within
the same rack and inter-rack interconnects with the memory hierarchies
are required.

Also, performance and reliability design constraints for exascale
storage systems are significant challenges for HPC system designers.
High performance I/O is an important aspect, because storing and
retrieving such large amounts of data can greatly affect the overall
performance of applications. Finally, it is important to characterize
the demands that exascale applications exert on the different components
of an exascale system.

The goal of PISCES workshop is to bring together researchers and
practitioners from academia and industry to discuss novel ways of
tackling all these aspects of exascale systems. Authors are invited to
submit high-quality papers representing original work in (but not
limited to) the following topics:

• Heterogeneous node designs: CPU, GPUs/ Accelerators and FPGAs
• On-chip and off-chip cache designs
• Interconnects for Exascale: electrical and optical networks
• Cache coherence in Exascale Computing
• Coherent DRAM-based cache designs
• Storage in Exascale systems
• Power saving policies at different hardware levels
• Hardware prototyping (FPGA hardware implementation and timing and
energy characterization)
• Applications characterization (bandwidth requirement, traffic,
scalability,...) for exascale computing


SUBMISSION INSTRUCTIONS

Submitted papers must not have been published or simultaneously
submitted elsewhere. Submissions in PDF format should not exceed 10
pages in the Springer LNCS style, which can be downloaded from the
Springer Web site. The 10 pages limit is a hard limit. It includes
everything (text, figures, references) and will be strictly enforced by
the submission system. Complete LaTeX sources must be provided for
accepted papers. All submitted research papers will be peer-reviewed.
Only contributions that are not submitted elsewhere or currently under
review will be considered. Although we are accepting papers with less
than 10 pages, it is important to note that only accepted 10-page papers
are eligible for publication in the workshop’s proceedings, published by
Springer in the ARCoSS/LNCS series. Authors of accepted papers will have
to sign a Springer copyright form. Papers should be submitted through
EasyChair. See the Euro-Par 2017 and PISCES 2017 websites for further
information about PISCES 2017 and submission details.


JOURNAL SPECIAL ISSUE

Authors of the best papers presented in the workshop will be invited to
extend their work and submit it to a special issue in the JCR-indexed
international journal “Concurrency and Computation: Practice &
Experience”. The special issue details can be found at the PISCES 2017 
website.


IMPORTANT DATES

May     12, 2017	Paper submission deadline (extended)
June    16, 2017	Notification of acceptance
October  3, 2017	Camera-ready due
August  29, 2017	Workshop date


WORKSHOP CO-CHAIRS

- Julio Sahuquillo, Universitat Politècnica de València, Spain
- Manuel E. Acacio, Universidad de Murcia, Spain

PROGRAM COMMITTEE

- Francisco J. Alfaro, Universidad de Castilla La Mancha, Spain
- Sandro Bartolini, Università di Siena, Italy
- Angelos Bilas, FORTH, Greece
- José L. Bosque, Universidad de Cantabria, Spain
- João Canas Ferreira, Universidade do Porto, Portugal
- Nikolaos Chrysos, FORTH, Greece
- Giorgos Dimitrakopoulos, Democritus University of Thrace, Greece
- Pierfrancesco Foglia, Università di Pisa, Italy
- David Kaeli, Northeastern University, USA
- Sonia López-Alarcón, Rochester Inst. of Technology, USA
- Javier Navaridas, University of Manchester, UK
- Juan Piernas, Universidad de Murcia, Spain
- Antoni Portero, Technical University of Ostrava, Czech Republic
- Salvador Petit, Universitat Politècnica de València, Spain