[hpc-announce] [CFP] DEADLINE EXTENSION - JPDC Special Issue on Systems for Learning, Inferencing, and Discovering (SLID)

Tumeo, Antonino Antonino.Tumeo at pnnl.gov
Sat Mar 25 13:50:05 CDT 2017

[Apologies if you receive multiple copies of this CFP]


--- Call for Papers
Journal of Parallel and Distributes Computing (JPDC)
Special Issue on Systems for Learning, Inferencing, and Discovering (SLID)

Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security.  Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This special issue seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

* Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors
*  Network architectures and interconnect (including high-radix networks, optical interconnects)
* Novel memory architectures and designs (including processors-in memory)
* Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing)
* Modeling, simulation and evaluation of novel architectures with irregular workloads
* Innovative algorithmic techniques
* Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
* Impact of irregularity on machine learning approaches
* Parallelization techniques and data structures for irregular workloads
* Data structures combining regular and irregular computations (e.g., attributed graphs)
* Approaches for managing massive unstructured datasets (including streaming data)
* Languages and programming models for irregular workloads
* Library and runtime support for irregular workloads
* Compiler and analysis techniques for irregular workloads
* High performance data analytics applications, including graph databases

This special issue solicits novel, unpublished work, and previously published, but significantly extended, work.

In particular, we invite extended submissions from the 2015 and 2016 editions of IA^3, the SC Workshop on Irregular Applications: Architectures and Algorithms.

---  Timeline 

Submission deadline: April 21, 2017 (NEW!!!! - HARD DEADLINE)
First round reviews: during June 2017 (early summer)
Revisions: and second round reviews – during August 2017 (late summer)
Final decisions: October/November 2017 (fall)

--- Guest Editors

Dr. Antonino Tumeo,
Senior Research Scientist
Pacific Northwest National Laboratory
Antonino.Tumeo at pnnl.gov

Dr. John Feo,
Director, Northwest Institute of Advanced Computing (NIAC), Pacific Northwest National Laboratory (PNNL)
john.feo at pnnl.gov

Dr. Oreste Villa,
Senior Research Scientist
NVIDIA Research
ovilla at nvidia.com

--- Submission Guidelines

All manuscripts submission and review will be handled by Elsevier Editorial System http://ees.elsevier.com/jpdc.  
All papers should be prepared according to JPDC Guide for Authors. It is important that authors select SI: SLID when they reach the “Article Type” step in the submission process.

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