[hpc-announce] Hot Interconnects 2017 CFP

[Grant, Ryan Eric (-EXP)]

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                                 CALL FOR PAPERS
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        25th International Symposium on High Performance Interconnects 2017
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                Ericsson, Santa Clara, California, August 23-25, 2017
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* Paper abstract deadline:     May 5th, 2017
* Submission deadline:         May 12th, 2017
* Notification of acceptance:  June 9th, 2017

Hot Interconnects is the premier international forum for researchers and
developers 
of state-of-the-art hardware and software architectures and
implementations for
interconnection networks of all scales, ranging from multi-core on-chip
interconnects 
to those within systems, clusters,data centers, and clouds. This yearly
conference 
is attended by leaders in industry and academia. The atmosphere provides
for a wealth 
of opportunities to interact with individuals at the forefront of this
field.

Themes include cross-cutting issues spanning computer systems, networking
technologies, and communication protocols for high-performance
interconnection 
networks. This conference is directed particularly at new and exciting
technology and
 product innovations in these areas. Contributions should focus on real
experimental 
systems, prototypes, or leading-edge products and their performance
evaluation. In 
past year¹s the best papers on interconnect microarchitecture have been
invited to 
submit extended versions of their papers to a special edition of IEEE
Micro, we are 
pursing this once again this year.

Building on last year's successful technical program comprising keynotes,
technical 
sessions, and panels on networking for datacenters and high-performance
computing, 
the 2017 edition of Hot Interconnects is generously hosted by Ericsson at
their 
campus in Santa Clara, CA.

This year's conference focuses on HPC and Hyperscale Data Centers
Interconnects and 
their use in traditional and non-traditional applications, such as large
scale 
machine learning. We hope you can join us there.

We invite paper submissions across a wide range of topics and levels,
ranging from 
fundamentals to the latest advances in hot topic areas.

Topics of interest include, but are not limited to:

* Novel and innovative interconnect architectures
* Multi-core processor interconnects
* System-on-Chip Interconnects
* Advanced chip-to-chip communication technologies
* Optical interconnects
* Protocol and interfaces for inter-processor communication
* Survivability and fault-tolerance of inter-connects
* High-speed packet processing engines and network processors
* System and storage area network architectures and protocols
* High-performance host-network interface architectures
* High-bandwidth and low-latency I/O
* Pb/s switching and routing technologies
* Innovative architectures for supporting collective communication
* Novel communication architectures to support cloud & grid computing
* Centralized and distributed cloud interconnects
* Requirements driving high-performance inter-connects
* Traffic characterization for HPC systems and commercial data centers
* Software-defined networking and software overlay networks
* Software for network bring-up, configuration and performance management
  (OpenFlow, OpenSM)
* Data Center Networking

SCHEDULE AND SUBMISSION PROCEDURE:

* Paper abstract deadline:      May 5th, 2017
* Submission deadline:          May 12th, 2017
* Notification of acceptance:   June 9th, 2017
* Symposium:                    August 23-24, 2017
* Tutorials:                    August 25, 2017

This year we invite papers to be submitted either as regular, long papers
(6-8 pages) or as short papers (3-4 pages). Short papers could
be positional papers, industry papers, or papers describing
hot-off-the-press breaking research results, and will judged accordingly
and independently from the regular long papers.

* Papers need sufficient technical detail to judge quality and
  suitability for presentation.
* Submissions should include title, author, abstract,
  and paper in double-column, IEEE format.
* Long paper limit: 8 pages, single-spaced, 2 columns.
* Short paper limit: 4 pages, single-spaced, 2 columns.
* Papers should be submitted electronically through EasyChair at
https://www.easychair.org/conferences/?conf=hoti25
* Paper title and abstract should be submitted by May 5th.
* Full paper manuscript should be submitted by May 12th.
* Accepted papers will be published in proceedings by the
  IEEE Computer Society.
* Regular paper presentations are 30-minute talks in a
  single-track conference format.

AWARDS: 

An award will be given to the best student paper. To be eligible for the
best paper 
award at least one of the paper authors must be a full-time student at the
time of 
submission. In addition, HotI will provide Student Travel Awards.
Information on travel
awards can be found on our web site.

GENERAL CHAIRS
Ada Gavrilovska, Georgia Tech
Eitan Zahavi, Mellanox

TECHNICAL PROGRAM CHAIRS
Jitu Padhye, Microsoft
Ryan Grant, Sandia National Laboratories

Please contact us at info at hoti.org if you have any questions.

Go to the Hot Interconnects web site for updates: www.hoti.org
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