[hpc-announce] [CFP] First Workshop on Computer Architecture Research with RISC-V (CARRV 2017)

[Ramon Bertran]

We are pleased to announce the call for papers for the First 
Workshop on Computer Architecture Research with RISC-V 
(CARRV 2017), co-located with IEEE MICRO. The CARRV workshop 
will be held on October 14, 2017 in Boston, MA.

CARRV brings together researchers in fields related to computer 
architecture, compilers, and systems for technical exchange on 
using RISC-V in computer architecture research.  Submission of 
early work is encouraged. The topics of specific interest for 
the workshop include, but are not limited to:

* RISC-V simulation/emulation infrastructures, including ports 
  of existing infrastructures
* Easily modifiable RISC-V RTL cores to support research
* Whole-SoC simulators/emulators and/or models built around RISC-V
* RISC-V-based research prototypes
* Machine-readable formal models and verification methodologies
* Compiler toolchains and operating system ports to support systems research
* Security architecture research
* Memory model research
* Quantitative comparison of RISC-V with other ISAs

The workshop is intended to be highly interactive with an open 
session discussing experiences with using the current state of the
RISC-V ecosystem for architecture research and what directions 
to take to improve it.

Important Dates:

* Abstract submission deadline August 1, 2017
* Full paper submission deadline: August 8, 2017

Full details are available at https://carrv.github.io. Please consider 
submitting a paper to CARRV. Please also consider submitting a talk 
proposal for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas 
California on November 28-30, 2017. The CFP for the 7th RISC-V Workshop 
will be out very shortly.