[hpc-announce] UPDATED: The 13th International Workshop on High-Performance, Power-Aware Computing (HPPAC'17) Now accepting short papers

Manzano, Joseph B Joseph.Manzano at pnnl.gov
Thu Jan 19 13:57:53 CST 2017

The 13th International Workshop on High-Performance, Power-Aware Computing (HPPAC'17)

Program co-chairs:   Shuaiwen Leon Song, Pacific Northwest National Lab
                                         Richard Vuduc, Georgia Tech
Publicity Chair:           Shirley Moore, Oak Ridge National Laboratory

Proceedings Chair:    Joseph Manzano, Pacific Northwest National Lab


To be held on Monday, May 29th, 2017, in conjunction with the 31st IEEE International Parallel and Distributed Symposium (IPDPS 2017).

Power and energy are now recognized as first-order constraints in high-performance computing.  Optimizing performance under power and energy bounds requires coordination across not only the software stack (compilers, operating and runtime systems, job schedulers) but also coordination with cooling systems and outwards to electrical suppliers.  As we continue to move towards exascale and extreme scale computing, understanding how power translates to performance becomes an increasingly critical problem.

The purpose of this workshop is to provide a forum where cutting-edge research in the above topic can be shared with others in the community. As such, while we welcome full (10 page) papers as in previous years, we are now also soliciting short papers (4 pages max).  While both should address power aware computing issues, short papers will be judged primarily on their interest to the community.  As such, these may be position papers, initial results, open problems, software announcements, or interesting work that does not reach the level of a full-paper treatment. All papers will be subject to single-blind peer review, and the quality of
both the short and standard papers is expected to be high.

Topics of particular interest include (but are not limited to):

* Performance optimization under node, job, cluster and site power bounds
* Power/performance tradeoffs across accelerators, processors and DRAM
* Cooling/performance tradeoffs
* Translating budgetary bounds into power and energy bounds.
* Power-efficient system design, from computer center to silicon
* Effects of compiler optimizations on application power and energy efficiency
* Power- and energy-aware job schedulers, runtime systems and operating systems
* Models of power and performance, from processors and components to computer centers
* Evaluations of hardware power and energy controls

Submission Guidelines

We invite two kinds of submissions to this workshop: (1) Full-length research papers (10-page limit); (2) Short papers (4-page limit), which can take the form of position papers, experience reports, or power and energy characterizations of current systems. Papers should not exceed ten (or four) single-spaced pages (including figures, tables and references) using 12-point font on 81⁄2x11-inch pages. Submissions will be judged on correctness, originality, technical strength, significance, presentation quality, and relevance. Submitted papers should not have appeared in or be under consideration for another venue. A full peer-review process will be followed with each paper being reviewed by at least three members of the program committee.
Submissions should follow the IEEE Conference Proceedings templates found at http://www.ieee.org/conferences_events/conferences/publishing/templates.html Camera-ready copy will need to conform to IPDPS guidelines; these will be announced during author notification.

Important dates

Paper Submission: January 29th, 2017
Paper Notification: February 22nd, 2017
Final Paper Due: March 7th, 2017

Program Committee
-              Dongyoon Lee, Virginia Tech, USA
-              Torsten Wilde, Leibniz Supercomputing Centre, Germany
-              Jee Choi, IBM, USA
-              Ryan Friese, Pacific Northwest National Laboratory, USA
-              Kevin Barker, Pacific Northwest National Laboratory, USA
-              Thomas Ilsche, Technische Universitat Dresden, Germany
-              Koji Inoue, Kyushu University, Japan
-              Suzanne Rivoire, Sonoma State University, USA
-              Michael Bader, Institut für Informatik, Technische Universität München, Germany
-              Natalie Bates, Energy Efficient HPC Working Group, USA
-              Sunita Chandrasekaran, University of Delaware, USA
-              Lizhong Chen, Oregon State University, USA
-              Joseph Greathouse, AMD, USA
-              Matthias Maiterth, Ludwig Maximilians Universitat Munchen, Germany
-              Aniruddha Marathe, University of Arizona, USA
-              Shirley Moore, Oak Ridge National Laboratory, USA
-              Barry Rountree, Lawrence Livermore National Laboratory, USA
-              Bo Wang, RWTH Aachen University, Germany
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