[hpc-announce] 6th ALCHEMY Track on Many-core Programming Issues (Part of ICCS 2018) CfP

[CUDENNEC Loic]

Call for Paper

              6th ALCHEMY Track, as part of ICCS 2018

              Architecture, Languages, Compilation and
        Hardware support for Emerging ManYcore systems

          https://sites.google.com/site/alchemyworkshop/

Important Dates:
Submission deadline: 31 January, 2018
Venue: 11-13th June, 2018, Wuxi, China


The future aims toward increasing parallelism and heterogeneity of
systems to tackle the so-called power-wall while permitting a roadmap
of increased performance. Several challenges rise for programming such
systems. The ALCHEMY workshop goal is to show some of these relevant
challenges and finding ways to tackle them, while permitting programmers
to focus on important part of application designs and letting compilers
or runtime optimization do most of the work toward good performance.

The ALCHEMY workshop is the Many-core track of ICCS. It is also a good
place of exchange between the traditional HPC domain of research and
all the emerging HPES (High Performance Embedded Systems) domain, since
the programming issues are mostly the same, with a relatively high
cost of communication and the difficulty to program hundreds of cores
often under performance and power usage constraints.

Original high quality submission are encouraged on all topics related to
many-core programming issues including (but not limited to):

* High-level Programming
 * Programming models and languages for many-cores
 * Compilers for programming languages
 * Runtime generation for parallel programming on manycores
 * Handling heterogeneity in many-cores

* Operational research and optimizations
 * Application, runtime, system and hardware sizing
 * Task scheduling
 * Task placement, application mapping

* System and runtime
 * New operating systems, dedicated OS
 * Dedicated runtimes for manycores
 * Shared memory, data consistency models and protocols

* Hardware architecture
 * Architecture support for massive parallelism management
 * Enhanced communications

* Security
 * Accelerators for security
 * Crypto systems for manycores

* In-situ systems and user experimentations
 * User feedback on existing manycore architectures
 * Many-core integration within HPC systems (micro-servers)
 * Coping with heterogeneity


All accepted papers will be included in the Springer Lecture Notes in
Computer Science (LNCS) series and indexed by Scopus, EI Engineering Index,
Thomson Reuters Conference Proceedings Citation Index
(included in ISI Web of Science), and several other indexing services.


General Chair
Loïc CUDENNEC, CEA, LIST, France
Stéphane LOUISE, CEA, LIST, France

Program Chair and Program Committee
TBA




--
Loïc CUDENNEC
http://www-list.cea.fr
http://www.cudennec.fr/
CEA, LIST, Nano-INNOV / Saclay
PC 172, 91191 Gif-sur-Yvette CEDEX
+33 1 69 08 00 58