[hpc-announce] 7th AsHES Workshop Co-Located with IPDPS 2017 - CALL FOR PAPERS

Sunita Chandrasekaran sunisg123 at gmail.com
Wed Sep 28 20:32:30 CDT 2016


The Seventh International Workshop on Accelerators and Hybrid Exascale
Systems (AsHES)
May 29th, 2017

To be held in conjunction with
31st IEEE International Parallel and Distributed Processing Symposium
Buena Vista Palace Hotel, Orlando, Florida, USA

Workshop Scope and Goals
Current and emerging systems are deployed with heterogeneous architectures
accelerators of more than one type (e.g., GPGPU, Intel® Xeon Phi™, FPGA)
with hybrid processors of both lightweight and heavyweight cores (e.g., APU,
big.LITTLE). Such architectures also comprise hybrid memory systems equipped
with stacked/hierarchical memory and non-volatile memory in addition to
DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and
heterogeneous designs on the hardware systems, porting applications,
compiler optimizations, and developing programming environments for current
emerging systems. It seeks to ground accelerator research through studies of
application kernels or whole applications on such systems, as well as tools
libraries that improve the performance and productivity of applications on
these systems.

The goal of this workshop is to bring together researchers and practitioners
who are involved in application studies for accelerators and other
heterogeneous systems, to learn the opportunities and challenges in future
design trends for HPC applications and systems.

Topics of interest for workshop submissions include (but are not limited

 * Strategies for programming heterogeneous systems using high-level models
   such as OpenMP, OpenACC, low-level models such as OpenCL, CUDA;
 * Methods and tools to tackle challenges in scientific computing at extreme
 * Strategies for application behavior characterization and performance
   optimization for accelerators;
 * Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon
   and future heterogeneous platforms;
 * Models of application performance on heterogeneous and accelerated HPC
 * Compiler Optimizations and tuning heterogeneous systems including
   parallelization, loop transformation, locality optimizations,
 * Implications of workload characterization in heterogeneous and
   architecture design;
 * Benchmarking and performance evaluation for accelerators;
 * Tools and techniques to address both performance and correctness to
   application development for accelerators and heterogeneous processors;
 * System software techniques to abstract application domain-specific
   functionalities for accelerators;

Important Dates (AoE)
Paper Submission: Jan. 13, 2017
Paper Notification: Feb. 15, 2017
Camera-Ready: Feb. 25, 2017

The proceedings of this workshop will be published electronically together
with IPDPS proceedings via the IEEE Xplore Digital Library.

Papers Submission Guidelines
Papers should present original research and should provide sufficient
background material to make them accessible to the broader community.

Submitted manuscripts may not exceed 10 single-spaced double-column pages
10-point size font on 8.5x11 inch pages (IEEE conference style), including
figures, tables, and references.  See the style templates for latex or word

Submissions will be judged based on relevance, significance, originality,
correctness and clarity.

Submission site: https://easychair.org/conferences/?conf=ashes17

Journal Special Issue

Keynote Speaker
Tim Mattson (Intel) will give a keynote speech at AsHES 2017.

Best Paper Award

Steering Committee
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada
James Dinan, Intel Corporation

General Chair
Sunita Chandrasekaran, University of Delaware, USA

Program Co-Chairs
Antonio J. Peña, Barcelona Supercomputing Center, Spain
Sangmin Seo, Argonne National Laboratory, USA

Program Committee
Ashwin Aji, AMD, USA
James Beyer, NVIDIA Corporation, USA
Huimin Cui, Institute of Computing Technology, CAS
Anthony Danalis, University of Tennessee, USA
Khaled Hamidouche, The Ohio State University, USA
Jeff Hammond, Intel Labs, USA
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Hennry Jin, NASA, USA
Guido Juckeland, HZDR, Germany
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Seyong Lee, Oak Ridge National Laboratories, USA
Dong Li, University of Calfornia, Merced, USA
John Lidel, Texas Tech University, USA
Piotr Luszczek, University of Tennessee, USA
Naoya Maruyama, RIKEN AICS, Japan
Stephen Olivier, Sandia Nationl Lab, USA
Kelly Shaw, University of Richmond, USA
Xipeng Shen, North Carolina State University, USA
Min Si, Argonne National Laboratory, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Yongpeng Zhang, Stone Ridge Technology, USA

Please send any queries about the AsHES workshop to ashes at mcs.anl.gov
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