[hpc-announce] E2SC 16 @ SC EXTENDED DEADLINE: September 9th, 2016

Manzano, Joseph B Joseph.Manzano at pnnl.gov
Thu Sep 1 18:20:18 CDT 2016

                       4th International Workshop on
                    Energy Efficient SuperComputing (E2SC)
                           November 14th, 2016
         Held in conjunction with SC'16, Salt Lake City, Utah, USA
                        November 13th-18th 2016

                            Call For Papers

------------- EXTENDED DEADLINE FOR SUBMISSIONS: September 9th, 2016 ----------------------


We will be ushering in an era with power and energy consumption as the
primary concerns for scalable computing in the exascale era and beyond. To
achieve viable high performance, revolutionary methods are required with a
stronger integration among hardware features, system software and applications.
Equally important are the capabilities for fine-grained spatial and temporal
measurement and control to facilitate energy efficient computing across all
layers. Current approaches for energy efficient computing rely heavily on power
efficient hardware in isolation. However, it is pivotal for hardware to expose
mechanisms for energy efficiency to optimize power and energy consumption for
various workloads and to reduce data motion, a major component of energy use.
At the same time, high fidelity measurement techniques, typically ignored in
data-center level measurement, are of high importance for scalable and energy
efficient inter-play in different layers of application, system software and

This workshop seeks to address important energy efficiency aspects in the
HPC community that have not been previously addressed in the data center or
cloud computing communities. Emphasis is given to the applications view
related to
significant energy efficiency improvements and to the required
hardware/software stack that must include necessary power and performance
measurement and analysis harnesses.

Current tools are often limited by hardware capabilities and their lack of
information about the characteristics of a given workload/application. In the
same manner, hardware techniques, like dynamic voltage frequency scaling, are
often limited by their granularity (very coarse power management) or by their
scope (a very limited system view). More rapid realization of energy savings
will require significant increases in measurement resolution and optimization
techniques.  Moreover, the interplay between performance, power and
reliability add another layer of complexity to this already difficult group of

Workshop Focus

We encourage submissions in the following areas:

- Tools for analyzing power and energy with different granularities and
  scope from hardware (e.g. component, core, node, rack, system) or
  software views (e.g. threads, tasks, processes, etc) or both.

- Techniques that enable power and energy optimizations at different
  scale levels for HPC systems.

- Integration of power aware techniques in applications and throughout
  the software stack of HPC systems.

- Characterization of current state-of-the-art HPC system and
  applications in terms of Power.

- Disruptive hardware or infrastructure technologies for energy-efficient

- Analysis of future technologies that will provide improved energy
  consumption and management on future HPC systems.

- Tools and techniques for exploring trade-offs between energy efficiency
  and resilience.

Organizing Committee

General Chairs:    Kirk Cameron, Virginia Tech, USA
                   Adolfy Hoisie, PNNL, USA
                   Darren Kerbyson, PNNL, USA
                   David Lowenthal, Arizona State University, USA
                   Dimitrios S. Nikolopoulos,Queen's University of Belfast,UK
                   Sudha Yalamanchili, Georgia Institute of Technology, USA

Program Chair:     Kevin Barker, PNNL, USA
                   Rong Ge, Marquette University, USA

Publicity Chair:   Joseph Manzano, PNNL, USA

European Liaison:  Michele Weiland, EPCC, UK

Proceedings Chair: Andres Marquez, PNNL, USA

Provisional Program Committee

Natalie Bates                          Energy Efficient HPC Working Group, USA
Laura Carrintgton                  San Diego Supercomputing Center, USA
Sunita Chandrasekaran       University of Delaware, USA
Vladimir Getov                       University of Westminster, UK
Roberto Gioiosa                     Pacific Northwest National Lab, USA
Eric van Hensbergen            ARM, USA
Karen Karavanic                     Portland State University, USA
Lennart Johnsson,                University of Houston, USA
Hyesoon Kim                           Georgia Tech, USA
James Laros,                            Sandia National Laboratory, USA
Dong Li                                       Oak Ridge National Lab, USA
Aniruddha Marathe              Lawrence Livermore National Lab, USA
Benoit Meister                        Reservoir Labs, USA
Lenny Oliker                             Lawrence Berkeley National Lab, USA
Tapasya Patki                           Lawrence Livermore National Lab, USA
Barry Rountree                       Lawrence Livermore National Lab, USA
Sameer Shende                      University of Oregon, USA
Shauwein (Leon) Song         Pacific Northwest National Lab, USA
Nick Wright                               Lawrence Berkeley National Lab, USA

Important Dates

Paper Submission            Extended to 9th September 2016
Paper Notification           23rd September 2016
Final Papers Due              3rd October 2016
Conference Date             14th November 2016

Submission Guidelines

Papers should not exceed eight single-space pages (including figures, tables
and references) using a 10-point on 8.5x11-inch pages. Submissions will be
judged on correctness, originality, technical strength, significance,
presentation quality and appropriateness. Submitted papers should not have
appeared in or under consideration for another venue. A full peer-review
processes will be followed with each paper being reviewed by at least 3
members of the program committee. Submissions will be made through EasyChair
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