[hpc-announce] MULTIPROG-2017: Deadline Extension (new deadline is November 4th)

Miquel Pericàs miquelp at chalmers.se
Sat Oct 22 02:46:20 CDT 2016



The Tenth International Workshop on
Programmability and Architectures for Heterogeneous Multicores

To be held in conjunction with:
the 12th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)
Stockholm, Sweden, January 24, 2017

Workshop website: http://research.ac.upc.edu/multiprog/

Goal of the Workshop

Computer manufacturers have embarked on the many-core roadmap, promising to
more and more cores/hardware threads on their chips. The ever-increasing
of cores and heterogeneity in architectures has placed new burdens on the
programming community. Software needs to be parallelized and optimized for
accelerators such as GPUs in order to take advantage of the new breed of
multi-/many-core computers. As a result, progress in how to easily harness
computing power of multi-core architectures is in great demand.

The tenth edition of the MULTIPROG workshop aims to bring together
interested in programming models, runtimes, and computer architecture. The
workshop's emphasis is on heterogeneous architectures and covers issues
such as:

    * How can future parallel programming models improve software

    * How should compilers, runtimes and architectures support programming
      models and emerging applications?

    * How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results,
etc., and is not intended to prevent later publication of extended papers.
Informal proceedings with accepted papers will be made available at the
and online at the workshop’s web page http://research.ac.upc.edu/multiprog/.

Topics of interest
Papers are sought on topics including, but not limited to:
    * Multi-core architectures
        o Architectural support for compilers/programming models
        o Processor (core) architecture and accelerators, in particular GPUs
        o Memory system architecture
        o Performance, power, temperature, and reliability issues
    * Heterogeneous computing
        o Algorithms and data structures for heterogeneous systems
        o Applications for heterogeneous computing and real-time graphics
    * Programming models for multi-core architectures
        o Language extensions
        o Run-time systems
        o Compiler optimizations and techniques
    * Benchmarking of multi-/many-core architectures
        o Tools for discovering and understanding parallelism
        o Tools for understanding performance and debugging
        o Case studies and performance evaluation

Important dates
Paper submission: November 4, 2016
Author notification: November 27, 2016

Paper submission
MULTIPROG accepts contributions of regular research papers and short
papers describing early research on emerging topics. When preparing your
submission please adhere to the following format specification:

* Regular research papers:

Regular research papers should preferably use LNCS format (up to 12 pages,
including references). Single column (up to 12-Pages) or double column (up
6-pages) formats are also accepted.

* Short position papers:

Short position papers should preferably use LNCS format (4-6 pages, not
including references). Single column (4-6 pages) or double column (2-3
formats are also accepted. Papers in this category should explicitly
"Position Paper:" in front of the title of their manuscript.

The authors of the accepted papers will be requested to provide the final
version of their paper in LNCS format. Please use the templates below:

* LNCS Latex template: ftp://ftp.springer.de/pub/tex/
* Word template: ftp://ftp.springer.de/pub/tex/

Submission link: https://easychair.org/conferences/?conf=multiprog2017

Miquel Pericàs            Chalmers         Sweden   miquelp[at]chalmers.se
Vassilis Papaefstathiou   FORTH-ICS        Greece   vaspap[at]chalmers.se
Oscar Palomar             U. Manchester    UK       oscar.palomar[at]
Ferad Zyulkyarov          BSC              Spain    ferad.zyulkyarov[at]

Program committee
Abdelhalim Amer         Argonne National Lab            USA
Ali Jannesari           UC Berkeley                     USA
Avi Mendelson           Technion                        Israel
Chris Adeyeni-Jones     ARM                             UK
Christos Kotselidis     University of Manchester        UK
Dong Ping Zhang         AMD                             USA
Håkan Grahn             Blekinge TH                     Sweden
Hans Vandierendonck     Queen’s University Belfast      UK
Kenjiro Taura           University of Tokyo             Japan
Magnus Själander        NTNU                            Norway
Oscar Plata             University of Malaga            Spain
Pedro Trancoso          University of Cyprus            Cyprus
Polyvios Pratikakis     FORTH-ICS                       Greece
Roberto Gioiosa         PNNL                            USA
Sasa Tomic              IBM Research                    Switzerland
Timothy G. Mattson      Intel                           USA
Trevor E. Carlson       Uppsala University              Sweden
Yungang Bao             ICT-CAS                         China

Workshop site
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