[hpc-announce] Call for Papers: TMSCS Special Issue on Advances in Parallel Graph Processing

Kalyanaraman, Ananth ananth at eecs.wsu.edu
Fri Nov 11 10:39:42 CST 2016

IEEE Transactions on Multi-Scale Computing Systems
Special Issue on Advances in Parallel Graph Processing: Algorithms, Architectures and Application Frameworks

Ananth Kalyanaraman, Washington State University, Pullman, WA, USA ananth at eecs.wsu.edu
Mahantesh Halappanavar, Pacific Northwest National Laboratory, Richland, WA, USA hala at pnnl.gov

In the sphere of modern data science and applications, graph algorithms have achieved a pivotal place in advancing the state of scientific discovery and knowledge. Nearly three centuries of ideas have made graph theory and its applications a mature area in computational sciences. Yet, today we find ourselves at crossroads between theory and application. Spurred by the digital revolution, data from over a diverse range of high throughput channels and devices, from across internet-scale applications, are starting to mark a new era in data-driven computing and discovery. Building robust graph models and implementing scalable graph application frameworks in the context of this new era are proving to be significant challenges. Concomitant to the digital revolution, we have also experienced an explosion in computing architectures, with a broad range of multicores, manycores, heterogeneous platforms and hardware accelerators (CPUs, GPUs) being actively developed and deployed within servers and multinode clusters. Recent advances have started to show that in more than one way, these two fields - graph theory and architectures - are capable of benefiting and in fact spurring new research directions in one another.

This special issue invites original research papers and authoritative position/survey papers that showcase cutting-edge research at the intersection of graph algorithms, graph applications and advanced architectures. Research topics of particular interest include (but not limited to):

-       Design of efficient, scalable architectures for graph-theoretic processing
-       Models and approaches for accelerated graph construction on chip
-       Characterization of graph operations based on computational characteristics
-       Hardware and algorithmic techniques to reduce latency and to improve data locality
-       Comparative evaluation of hardware architectures for different graph operations
-       Efficient approaches to utilize heterogeneous architectures for graph computing
-       Communication-reducing techniques and paradigms for large-scale graph applications
-       Power and energy efficiency of graph operations on chip
-       Processing dynamic graphs and graph streams on chip
-       High-end graph applications using high performance architectures and platforms

Open for submissions in ScholarOne Manuscripts:  February 1, 2017
Closed for submissions:                          March 1, 2017
Results of first round of reviews:               May 1, 2017
Submission of revised manuscripts:               July 1, 2017
Results of second round of reviews:              August 1, 2017
Publication materials due:                       September 1, 2017

Prospective authors are invited to submit their manuscripts electronically after the “open for submissions” date, adhering to the IEEE Transactions on Multi-Scale Computing Systems guidelines (http://www.computer.org/portal/web/tmscs/author). Please submit your papers through the online system (https://mc.manuscriptcentral.com/tmscs-cs) and be sure to select the special issue name. Manuscripts should not be published or currently submitted for publication elsewhere. Please submit only full papers intended for review, not abstracts, to the ScholarOne portal. If requested, abstracts should be sent by e-mail to the Guest Editors directly.

- Ananth Kalyanaraman

Associate Professor
Boeing Centennial Chair in CS
School of EECS
Washington State University
Pullman WA 99164-2752

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