[hpc-announce] First International Workshop on Communication Optimizations in HPC (COMHPC) @SC'16: Call For Participation

Akhil langer akhilanger at gmail.com
Sun Nov 6 11:16:40 CST 2016

First International Workshop on Communication Optimizations in HPC (COMHPC)


 In cooperation with ACM SIGHPC

co-located with

SC16: The International Conference for High Performance Computing,
Networking, Storage and Analysis

*CALL FOR PARTICIPATION**Friday, Nov 18, 2016* from *8:30am-12:10 p.m.* in
*355-D*(please check http://software.intel.com/en-
us/event/comhpc/2016/overview for more details about the workshop)

*Workshop Program*

8:30 – 9:15

Keynote: Bill Gropp (NCSA, UIUC) – Meeting the Communication Needs of
Scalable Applications

9:15 – 10:05

Technical Session 1:


Efficient Reliability Support for Hardware Multicast-based Broadcast in
GPU-enabled Streaming Applications

Ching-Hsiang Chu, Khaled Hamidouche, Hari Subramoni, Akshay Venkatesh,
Bracy Elton and Dhabaleswar Panda


Topology and affinity aware hierarchical and distributed load-balancing in

Francois Tessier, Emmanuel Jeannot and Guillaume Mercier


Extending a Message Passing Runtime to Support Partitioned, Global Logical
Address Spaces

D. Brian Larkins and James Dinan

10:05 – 10:30

Coffee break

10:30 – 12:10

Technical Session 2:


DISP: Optimizations towards Scalable MPI Startup

Huansong Fu, Swaroop Pophale, Manjunath Venkata and Weikuan Yu


Network Topologies and Inevitable Contention

Grey Ballard, James Demmel, Andrew Gearhart, Benjamin Lipshitz, Yishai
Oltchik, Oded Schwartz and Sivan Toledo


Topology-Aware Data Aggregation for Intensive I/O on Large-Scale

Francois Tessier, Venkatram Vishwanath, Preeti Malakar, Emmanuel Jeannot
and Florin Isaila


Scalable Hierarchical Aggregation Protocol SHArP: A Hardware Architecture
for Efficient Data Reduction

Richard Graham, Dror Goldenberg, Gil Bloch, Lion Levi, Alex Margolin, Gilad
Shainer and Alexander Shpiner


Topology-Aware Performance Optimization and Modeling of Adaptive Mesh
Refinement Codes for Exascale

Cy Chan, John Bachan, Joseph Kenny, Jeremiah Wilke, Vincent Beckner, Ann
Almgren and John Bell

 As HPC applications scale to large super-computing systems, their
communication and synchronization need to be optimized in order to deliver
high performance. To achieve this, capabilities of modern network
interconnect and parallel runtime systems need to be advanced and the
existing ones to be leveraged optimally. Participants at this workshop will
benefit from discussions, collaboration, and ideas that drive the design of
future peta/exa-scale systems and HPC applications.

*Organizing Committee:*

   - Michael Chuvelev (Intel, Russia)
   - Daniel Faraj (SGI, USA)
   - Maria Garzaran (UIUC and Intel, USA)
   - Akhil Langer (Intel, USA)
   - Malek Musleh (Intel USA)
   - Gengbin Zheng (Intel, USA)

*Program Committee:*

   - Ahmad Afsahi (Queen’s University, Canada)
   - George Almasi (IBM, USA)
   - Abhinav Bhatele (LLNL, USA)
   - Bill Gropp (University of Illinois Urbana-Champaign, USA)
   - Manish Gupta (Xerox Research Center, India)
   - Ram Huggahalli (Intel, USA)
   - Nikhil Jain (LLNL, USA)
   - David Lowenthal (University of Arizona, USA)
   - Vijay Pai (Google, USA)
   - D. K. Panda (Ohio State University, USA)
   - Sameh Sharkawi (IBM, USA)
   - Yogish Sabharwal (IBM, India)
   - Martin Schulz (LLNL, USA)
   - Bronis R. de Supinski (LLNL, USA)
   - Sayantan Sur (Intel, USA)
   - Michela Taufer (University of Delaware, USA)
   - Keith Underwood (Intel, USA)
   - Abhinav Vishnu (PNNL, USA)
   - Alan Wagner (University of British Columbia, Canada)
   - Xin Yuan (Florida State University, USA)

*Contact: *

Please email comhpc.org at gmail.com for any questions
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