[hpc-announce] [CFP] The 2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (REPARA 2016)

FRANCISCO JAVIER GARCIA BLAS fjblas at inf.uc3m.es
Tue Mar 15 11:35:41 CDT 2016

[Apologies if you got multiple copies of this email]

The 2nd International Workshop on Reengineering for Parallelism in
Heterogeneous Parallel Platforms (REPARA 2016)

Held in conjunction with IEEE ScalCom 2016

Toulouse, France
July 18-21, 2016

In recent years, traditional processors have not been able to directly
translate chip fabrication technology advances intro performance gains. To
keep satisfying the demand for computing power, there is a shift from
homogeneous machines to heterogeneous architectures combining different
kinds of processors (CPUs, GPUs, DSPs, FPGAs, and other accelerators).
While this approach has allowed significant performance and energy
efficiency benefits, heterogeneous systems are often highly difficult to
program with existing tools. To reduce the cost of system development,
reengineering techniques emerge as a solution which may help to balance
ease-of-development with better performance, better reliability, and lower
maintenance costs.

The RePara2016 workshop is organized in cooperation with the REPARA
European Project and it aims to join experts from related disciplines to
share recent advances in different areas contributing to better
transformation of new and legacy applications to different programming
models for diverse computing devices in the context of parallel
heterogeneous architectures.

Scope and Interest

Topics of interest include, but are not limited to:

- High-level parallel programming models, libraries and languages for
heterogeneous platforms
- Description languages for Heterogeneous Parallel Platforms
- Parallel patterns for Heterogeneous Platforms
- Autonomic management of Power/Performance tradeoffs
- Automated kernel identification and assessment
- Software refactoring approaches for parallel programming models
- Transformations from source code to reconfigurable hardware
- Integration of FPGA accelerators into refactored software
- Runtimes for software coordination in heterogeneous parallel platforms
- Performance modeling and prediction in heterogeneous parallel platforms
- Energy efficiency monitoring and prediction in heterogeneous parallel
- Software quality assessment in parallel programming models with special
attention to maintainability
- Applying partitioning and mapping for parallel heterogeneous computing
- Application experiences of refactoring to software in industrial domains

Journal Publication

Extended version of selected papers from the workshop will be invited by
the REPARA2016 program committee for publication, after further revision,
in an special issue of a Journal (approval pending).

Submission Instructions

Papers submitted to the workshop should be written in English conforming to
the IEEE Conference Proceedings Format (8.5″ x 11″, Two-Column). The paper
should be submitted through the workshop submission system (pending) at the
workshop website. The length of the papers should not exceed 8 pages.

Accepted and presented papers will be included into the IEEE Conference
Proceedings published by IEEE CS CPS and submitted to IEEE Xplore and CSDL.
Authors of accepted papers, or at least one of them, are requested to
register and present their work at the conference, otherwise their papers
will be removed from the digital libraries of IEEE CS after the conference.
Distinguished papers presented at the conference, after further revision,
will be recommended to special issues of reputable SCI/EI-indexed journals.

Submitting a paper to the workshop means that, if the paper is accepted, at
least one author should attend the workshop and present the paper.
Submitted papers must not substantially overlap with papers that have been
published or that are simultaneously submitted to a journal or a conference
with proceedings.


Please email inquiries concerning the workshop to J. Daniel Garcia (
josedaniel.garcia at uc3m.es) and Javier Garcia Blas (fjblas at inf.uc3m.es).

Dr. Javier García Blas
Computer Architecture, Communications and Systems Area.
Avda. de la Universidad, 30
28911 Leganés (Madrid), SPAIN
e-mail: fjblas at inf.uc3m.es
Phone:(+34) 916249143
FAX: (+34) 916249129
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.mcs.anl.gov/mailman/private/hpc-announce/attachments/20160315/fb14f84a/attachment-0001.html>

More information about the hpc-announce mailing list