[hpc-announce] Fwd: CFP: First Int'l Workshop on Communication Optimizations in HPC (COMHPC) @SC16, Deadline: August 19

Akhil langer akhilanger at gmail.com
Tue Jun 21 09:46:06 CDT 2016

First International Workshop on Communication Optimizations in High
Performance Computing (COMHPC)


In cooperation with ACM SIGHPC

 [image: Inline image 3]

Friday, November 18, 2016

co-located with

SC16: The International Conference for High Performance Computing,
Networking, Storage and Analysis

November 13-18, 2016


*Call for Papers:*

As HPC applications scale to large supercomputing systems, their
communication and synchronization need to be optimized in order to deliver
high performance. In order to achieve this, capabilities of modern network
interconnect and parallel runtime systems need to be advanced and the
existing ones to be leveraged optimally. The workshop will bring together
researchers and developers to present and discuss work on optimizing
communication and synchronization in HPC applications. This includes
state-of-the-art methodological and algorithmic advances in topology-aware
or topology-oblivious blocking and non-blocking collective algorithms,
offloading of communication to network interface cards, topology aware
process mappings for minimizing communication overhead on different network
topologies such as dragonfly, high-dimensional torus networks, fat trees,
optimizations for persistent communication patterns, studies and solutions
for inter-job network interference, overlapping of communication with
computation, optimizing communication overhead in the presence of process
imbalance, GPU-GPU and GPU-CPU communication. The workshop also aims at
bringing researchers together to foster discussion, collaboration and ideas
for optimizing communication and synchronization that drive design of
future peta/exa-scale systems and of HPC applications. In addition, we
expect that researchers and others looking for research directions in this
area will get up-to-date with the state of the art so that they can drive
their research in a manner that will impact the future of communication
methods in high performance computing.

*Topics of interest for workshop submissions include (but are not limited

Blocking and non-blocking collective operations

Topology-aware collective algorithms and process mappings

Neighborhood collective optimizations

Communication offloading design and optimizations (such as offloaded
triggered operations)

Modeling and simulation of traffic patterns (including collectives) for
generic/specific network topologies

Optimizations for persistent communication patterns

Inter-job network interference

Computation-communication overlap in HPC applications

Communication optimization in presence of process imbalance

Static/runtime tuning of collective operations

Scalable communication endpoints for many-core architectures

Communication optimizations on Peta/Exa-scale systems, heterogeneous
systems, and GPUs

Network congestion studies and mitigation methods

Machine learning to optimize communication

Communication aspects of GPGPU

Communication aspects of Graph Applications

Communication aspects of Fault Tolerance

*Important Deadlines:*

Submission deadline:              August 19, 2016 AOE

Notification of Acceptance:      September 25, 2016

Camera Ready copy:               October 5, 2016

Workshop Dates:                     November 18, 2016

*Paper Submission Guidelines:*

Papers must follow the ACM format (see
Submissions are limited to up to 10 pages. We also encourage submission of
work-in-progress and late-breaking ideas that illustrate promising results.
The 10-page limit includes figures, tables, and appendices, but does not
include references, for which there is no page limit. Papers should be
submitted electronically via EasyChair:
https://easychair.org/conferences/?conf=comhpc2016. Submitted papers should
not have appeared in or be under consideration for a different workshop,
conference or journal. Papers will be peer-reviewed by the Program
Committee for novelty, scientific merit, technical strength, originality,
quality of presentation and scope of the workshop. It is also expected that
at least one author of an accepted paper must register for and attend the
workshop. Accepted papers will be published in the workshop proceedings by
SIGHPC and made available in the ACM Digital Library and IEEE Xplore.

One outstanding paper selected by the Program Committee will be
awarded the *Best
Paper Award* (sponsored by Intel).

*Organizing Committee:*

Akhil Langer (Intel, USA)
Maria Garzaran (Intel, USA)

Gengbin Zheng (Intel, USA)
Malek Musleh (Intel, USA)
Daniel Faraj (Intel, USA)
Michael Chuvelev (Intel, Russia)

*Program Committee:*

Ahmad Afsahi (Queen’s University, Canada)

George Almasi (IBM, USA)

Abhinav Bhatele (LLNL, USA)

Bill Gropp (University of Illinois Urbana-Champaign, USA)

Manish Gupta (Xerox Research Center, India)

Ram Huggahalli (Intel, USA)

Nikhil Jain (LLNL, USA)

David Lowenthal (University of Arizona, USA)

Vijay Pai (Google, USA)

D. K. Panda (Ohio State University, USA)

Sameh Sharkawi (IBM, USA)

Yogish Sabharwal (IBM, India)

Martin Schulz (LLNL, USA)

Bronis Supinski (LLNL, USA)

Sayantan Sur (Intel, USA)

Michela Taufer (University of Delaware, USA)

Keith Underwood (Intel, USA)

Abhinav Vishnu (PNNL, USA)

Alan Wagner (University of British Columbia, Canada)

Xin Yuan (Florida State University, USA)

*Contact: *

Please email comhpc.org at gmail.com for any questions.

*** Please forward to anyone who might be interested ***
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