[hpc-announce] CCPE Journal Special Issue on Trends in High-Performance Interconnection Networks - Deadline approaching

Jesús Escudero Sahuquillo jesus.escudero at uclm.es
Tue Jul 19 03:20:02 CDT 2016


[Apologies if you received multiple copies of this CFP]

*** Deadline extended: July 28 (Hard deadline)

========================================================================

      Special Issue on Trends in High-Performance Interconnection Networks
                  in the Exascale and Big-Data Era

                  Wiley Journal of Concurrency and
                Computation: Practice and Experience

          http://hipineb.i3a.info/hipineb2016/special-issue/

========================================================================

GUEST EDITORS

  * Pedro Javier Garcia, University of Castilla-La Mancha, Spain
  * Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain

SCOPE

By the year 2023, High-Performance Computing (HPC) Systems are expected to
break the performance barrier of the Exaflop (10^18 FLOPS) while their
power consumption is kept at current levels (or incremented marginally),
what is known as the Exascale challenge.
In addition, more storage capacity and data-access speed is demanded to HPC
clusters and datacenters to manage and store huge amounts of data produced
by software applications, what is known as the Big-Data challenge. Indeed,
both the Exascale and Big-Data
challenges are driving the technological revolution of this decade,
motivating big research and development efforts from industry and academia.
In this context, the interconnection
network plays an essential role in the architecture of HPC systems and
datacenters, as the number of processing or storage nodes to be
interconnected in these systems is very likely to grow significantly to
meet the higher computing and storage demands. Besides, the capacity of the
network links is expected to grow, as the roadmaps of several
interconnect standards
forecast. Therefore, the interconnection network should provide a high
communication bandwidth and low latency, otherwise the network will become
the bottleneck of the entire system. In that regard, many design aspects
are considered when it comes to improve the interconnection network
performance, such as topology, routing algorithm, power consumption,
reliability and fault tolerance, congestion control, programming
models, control
software, etc.

All researchers and professionals, both from industry and academia, working
in the area of interconnection networks for scalable HPC systems and
Datacenters, and especially those
involved in Exascale performance and Big-Data, are encouraged to submit a
paper to this special issue.

TOPICS OF INTEREST

The list of topics covered by this Special Issue includes, but is not
limited to, the following:

* Interconnect architectures and network technologies for high-speed,
low-latency interconnects.
* Scalable network topologies, suitable for interconnecting a huge number
of nodes.
* Power saving policies in the interconnect devices and network
infrastructure, both at software and hardware level.
* Emerging ideas, work-in-progress and early, high-impact achievements.
* Good practices in the configuration of the network control software.
* Network communication protocols: MPI, RDMA, Hadoop, etc.
* APIs and support for programming models.
* Routing algorithms.
* Quality of Service (QoS).
* Reliability and Fault tolerance.
* Load balancing and traffic scheduling.
* Network Virtualization.
* Congestion Management.
* Applications and Traffic characterization.
* Modeling and simulation tools.
* Performance Evaluation.

Note that papers focused on topics that are too far from the design,
development and configuration of high-performance interconnects for HPC
systems and Datacenters (e.g., mobile networks, intrusion detection,
peer-to-peer networks or grid/cloud computing) will be automatically
considered as out of scope and rejected without review.

IMPORTANT DATES

Deadline for submissions:    Extended to July 28 (hard deadline)
First rounds of review:      September 7, 2016
Deadline for revised papers: October 7, 2016
Final decision notification: October 23, 2016
Camera Ready:                October 30, 2016
Estimated publication date:  January 31, 2017

All deadlines are set at 11:59 p.m. anywhere on Earth
(cf. http://wirelessman.org/aoe.html).

INSTRUCTIONS FOR AUTHORS

* This call is open for all contributions, but it also invites selected
papers from the 2nd edition of the HiPINEB workshop (
http://hipineb.i3a.info/hipineb2016).

* Authors must abide by the requirement of adding significant novelty to
the papers submitted to this special issue. Extended versions of conference
papers must contain at least 50% new content. Besides, it is mandatory to
attach a cover letter to any submission, explaining the main contributions
of the paper.

* Manuscripts should not exceed 25 pages in length.

* It is expected that submissions will align with the topics of interest
listed above.

* Manuscripts should accomplish the general rules defined at:
http://www.cc-pe.net/journalinfo/issues/2016.html#HiPINEB2016

* Papers should be submitted via Manuscript Central to special issue
“HiPINEB2016”: http://mc.manuscriptcentral.com/cpe

ADDITIONAL INFORMATION

For more information about this special issue or if you have any question,
please contact the guest editors at jesus.escudero at uclm.es or
pedrojavier.garcia at uclm.es
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.mcs.anl.gov/mailman/private/hpc-announce/attachments/20160719/774dbf1f/attachment-0001.html>


More information about the hpc-announce mailing list