[hpc-announce] DEADLINE EXTENSION (31.01.16) 12th ARCS Workshop on Dependability and Fault Tolerance (VERFE’16)

[Fechner, Bernhard]

Dear Sirs,

could you please consider the following CfP for publication?
Thank you.
Greetings from Germany,


Bernhard Fechner

======================== Call for Papers =======================================
12th Workshop on Dependability and Fault Tolerance (VERFE’16) in conjunction 
with ARCS 2016, Nuremberg, Germany, April 4th – 7th, 2016 
================================================================================

GI/ITG/GMA Technical Committee “Dependability and Fault Tolerance” (VERFE) and 
DFG Priority Program SPP 1500 “Dependable Embedded Systems”



Background and Focus
---------------------
Although the basic reliability of hardware and software components over the
decades has steadily grown, 
their increasing number still causes severe problems. 
Moreover, in recent years it can be observed that in an increasing number of
devices, e.g. cars, digital components are integrated into environments of other
physical components. 
Here the complexity of the interactions with these other components, 
as well as the limited accessibility of the digital ones create problems
with regard to maintaining a dependable operation of the entire system 
in case of faults or external disturbances. While this is not a problem 
with microprocessors, there, the ever shrinking feature sizes, 
the higher complexity, lower voltages, and higher clock frequencies 
increase the probability of design-, manufacturing-, and operational faults, 
making fault tolerance techniques in general purpose processors to be of
crucial importance in the future. 
As simple solutions (such as TMR) easily can get too expensive, 
the ability to trade increased reliability against performance/power
overhead will become important, resulting in light-weight fault tolerance 
techniques implemented in hardware, 
but controllable from higher software layers.

This workshop aims at presenting contributions and work-in-progress from the
research area of dependable and fault tolerant computing 
in order to bring together scientists working in related fields, especially
from the central European countries.

Topics
---------------------
Contributions on the topics of “Dependable Embedded Systems“ and
“Software-Controlled, Adaptive Fault Tolerance in Microprocessors” are of
particular interest; contributions on general topics of dependability and
fault tolerance are also welcome but not limited to: 

* reliability models for hardware and software
* modeling and simulation of fault-tolerant systems
* fault-tolerant systems and system components
* formal verification of systems
* testing of hardware and software
* fault treatment
* detection and correction of transient faults
* quantitative assessment of reliability improvements
* safety-critical applications
* timeliness problems
* dependability of networks
* dependability of embedded systems
* highly available systems
* dependable organic computing
* self-organization within redundant systems
* dependable ubiquitous and pervasive computing
* composability of dependable systems
* dependable mechatronic systems / micro systems
* dependability of mobile and wireless systems
* robustness and robustness metrics
* validation and verification
* fault models and fault model abstraction
* fault-injection techniques
* software-controlled fault tolerance
* on-chip backward recovery techniques (e.g. pipeline flush and re-execution)
* forward recovery techniques (notification of higher layers)
* fault-tolerant caches
* dynamic re-use of currently unused resources in processors for fault-tolerance



Information for Authors
-----------------------
Accepted papers will be published by VDE and are intended for IEEExplore.
The workshop will focus on research presentations as well as 
brainstorming sessions. 
Therefore, two kinds of contributions are welcome:
* research papers documenting results of scientific investigations and
* position papers proposing strategies or discussing open problems.


Deadlines:
-----------------------
Submission:   EXTENDED: January 31, 2016 
              (extended abstracts (3-4 pages) or full papers, PDF)
to:           bernhard.fechner at fernuni-hagen.de
Notification: February 15, 2016
Camera-ready: February 26, 2016 (max. 12 pages); 
              will appear in ARCS 2016 Workshop Proceedings. 

VERFE'16 Workshop site:  http://www3.cs.fau.de/arcs2016/download/CfP_VERFE.pdf 
Further information about ARCS 2016: http://www3.cs.fau.de/arcs2016


Workshop Chairs
-----------------------
B. Fechner, Univ. of Hagen, DE
K.-E. Großpietsch, St. Augustin, DE

Program Committee
-----------------------
L. Bauer, Karlsruhe Inst. of Technology, DE
F. Belli, Univ. of Paderborn, DE
R. Buchty, Karlsruhe Inst. of Technology, DE
K. Echtle, Univ. of Duisburg-Essen, DE
W. Ehrenberger, Univ. of Fulda, DE
R. Ernst, TU Braunschweig, DE
B. Fechner, Univ. of Hagen, DE
M. Gössel, Univ. of Potsdam, DE
K.-E. Großpietsch, St. Augustin, DE
J. Henkel, Karlsruhe Inst. of Technology, DE
J. Hursey, Oak Ridge National Lab., US
J. Keller, Univ. Hagen, DE
H.-D. Kochs, Univ. of Duisburg-Essen, DE
M. Lê, KUKA Augsburg, DE
P. Limbourg, Univ. of Duisburg-Essen, DE
M. Malek, Univ. of Lugano, CH
E. Maehle, Univ. of Lübeck, DE
M. Mock, Fraunhofer, St. Augustin, DE
E. Nett, Univ. of Magdeburg, DE
D. Nikolos, Univ. of Patras, DE
A. Pataricza, Univ. of Budapest, HU
F. Saglietti, Univ. of Erlangen-Nuremberg, DE
T. Sato, Univ. of Fukuoka, JP
M. Schulz, Lawrence Livermore National Lab., US
M. Shafique, Karlsruhe Inst. of Technology, DE
P. Sobe, HTW Dresden, DE
J. Sosnowski, Univ. of Warsaw, PL
A. Stopp, Daimler AG, Berlin, DE
C. Trinitis, TU Munich, DE
P. Tröger, TU Chemnitz, DE
T. Vierhaus, TU Cottbus, DE
M. Walter, Siemens AG, Nuremberg, DE
H. Wedde, TU Dortmund, DE
N. Wehn, TU Kaiserslautern, DE
J. Weidendorfer, TU Munich, DE
H.-Y. Youn, Univ. of Sungkyunkwan, KR
T. Yoneda, Univ. of Tokyo, JP
S. Zug, Univ. of Magdeburg, DE