[hpc-announce] NOCS 2016 - Deadline Extended - 10th IEEE/ACM International Symposium on Networks-on-Chip

[Maurizio Palesi]

[We apologise if you receive multiple copies of this CFP]

===> SUBMISSION DEADLINE EXTENDED <===

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			Call for Papers

10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
August 31 - September 2, 2016
Nara, Japan
		http://www.arc.ics.keio.ac.jp/nocs16
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	The International Symposium on Networks-on-Chip (NOCS) is the
premier event dedicated to interdisciplinary research on on-chip,
chip-scale, and multichip package scale communication technology,
architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and
applications from inter-related research communities, including
computer architecture, networking, circuits and systems, packaging,
embedded systems, and design automation. Topics of interest include,
but are not limited to:

NoC Architecture and Implementation:

1. Network architecture (topology, routing, arbitration)
2. NoC Quality of Service
3. Timing, synchronous/asynchronous communication
4. NoC reliability issues
5. Network interface issues
6. NoC design methodologies and tools
7. Signaling & circuit design for NoC links

NoC Analysis and Verification:

1. Power, energy & thermal issues (at the NoC, un-core and/or system-level)
2. Benchmarking & experience with NoC-based hardware
3. Modeling, simulation, and synthesis of NoCs
4. Verification, debug & test of NoCs
5. Metrics and benchmarks for NoCs

Novel NoC Technologies:

1. New physical interconnect technologies, e.g., carbon nanotubes, wireless
   NoCs, through-silicon, etc.
2. NoCs for 3D and 2.5D packages
3. Package-specific NoC design
4. Optical, RF, & emerging technologies for on-chip/in-package interconnects

NoC Application:

1. Mapping of applications onto NoCs
2. NoC case studies, application-specific NoC design
3. NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
4. NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
5. Scalable modeling of NoCs

NoC at the Un-Core and System-level:

1. Design of memory subsystem (un-core) including memory controllers,
   caches, cache coherence protocols & NoCs
2. NoC support for memory and cache access
3. OS support for NoCs
4. Programming models including shared memory, message passing and
   novel programming models
5. Issues related to large-scale systems (datacenters, supercomputers)
   with NoC-based systems as building blocks

On-Chip Communication Optimization:

1. Communication efficient algorithms
2. Multi/many-core communication workload characterization & evaluation
3. Energy efficient NoCs and energy minimization

	Electronic paper submission requires a full paper, up to 8
double-column IEEE format pages, including figures and references.
The program committee in a double-blind review process will evaluate
papers based on scientific merit, innovation, relevance, and presentation.
	Submitted papers must describe original work that has not been
published before or is under review by another conference or journal
at the same time. Each submission will be checked for any significant
similarity to previously published works or for simultaneous
submission to other archival venues, and such papers will be rejected.
Proposals for special sessions, tutorials, and demos are invited. Paper
submissions and demo proposals by industry researchers or engineers to
share their experiences and perspectives are also welcome.
	Please see the detailed submission instructions for paper
submissions, special session, tutorial, and demo proposals at the
submission page. Further information is available
via:http://www.arc.ics.keio.ac.jp/nocs16

Important Dates:

Abstract registration deadline		February 22, 2016 (Anywhere on Earth)
Full paper submission deadline		February 29, 2016 (Anywhere on Earth)
Notification of acceptance		April 8th, 2016
Final version due			May 18th, 2016

Organizing Committee

General Co-Chairs:
- Hideharu Amano (Keio University, Japan)
- Partha Pratim Pande (Washington State University, USA)
Technical Program Co-Chairs:
- Hiroki Matsutani (Keio University, Japan)
- Sriram Vangal (Intel, USA)
Publicity Co-Chairs:
- John Kim (Korea Advanced Institute of Science and Technology, Korea)
- Turbo Majumder (Intel, USA)
- Maurizio Palesi (Kore University, Italy)
Publication Chair:
- Umit Ogras (Arizona State University, USA)
Industry Chair:
- Yuichiro Ajima (Fujitsu Limited, Japan)
Special Sessions Co-Chairs:
- Michihiro Koibuchi (National Institute of Informatics, Japan)
- Sudeep Pasricha (Colorado State University, USA)
Tutorial Chair:
- Paul Bogdan (University of Southern California, USA)
Finance Chair:
- Ikki Fujiwara (National Institute of Informatics, Japan)
Registration Chair:
- Takashi Nakada (University of Tokyo, Japan)
Local Arrangements Chair:
- Shinya Takamaeda (Nara Institute of Science and Technology, Japan)
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