[hpc-announce] CfP: AISTECS workshop @ HiPEAC 2016

Bogdan Prisacari bpr at zurich.ibm.com
Mon Sep 21 11:35:42 CDT 2015

[Please accept our apologies if you receive multiple copies of this 

Call for Papers

1st International Workshop on
Advanced Interconnect Solutions and Technologies for Emerging Computing 

Associated with the
11th HiPEAC Conference on High Performance and Embedded Architecture and 
January 18–20, 2016, Prague, Czech Republic

This workshop is a new format blending the successful INA-OCMC workshop 
(nine editions
at HiPEAC) and the envelope-pushing Silicon Photonics workshop (two 
editions at HiPEAC)
into one combined instance.

Scalable interconnect architectures form the solid base on top of which 
future complex
computing platforms will be developed. The interconnect architecture 
should be as high
performance as its connecting nodes, thus enabling the expected 
exponential growth in
system concurrency. The number of nodes either on-chip or off-chip that 
need to
communicate in modern embedded and HPC systems is constantly increasing. 
This trend
poses significant challenges to the interconnection network designers that 
tackle a
multidimensional problem involving hardware and software components such 
as network
interfaces, switches, and communication library APIs.

At the same time, new usage models of mobile devices together with the 
convergence trend require that largely different operating conditions are 
by a single, deeply reconfigurable design. In this direction, 
heterogeneity could take the
form of runtime specialization rather than design time customization. 
manufacturing yield and device availability could be significantly 
improved by the device
capability to adapt to hardly predictable and even changing operating 
conditions at runtime. 

With Exascale systems on the horizon, we will be ushering in an era with 
power and energy
consumption as the primary concerns for scalable computing. To achieve 
viable high
performance, revolutionary methods are required with a stronger 
integration among
hardware features, system software and applications.

A main purpose of this workshop is to promote further research interests 
and activities on
Silicon Photonics and related topics in the perspective of its adoption in 
future high
performance systems and, in general, within future computing systems (from
servers/workstations down to embedded devices). In fact, Silicon Photonics 
poses in itself
crucial challenges and interesting design tradeoffs for being deployed in 
future computer
systems effectively, also in integration with other technologies. 
Furthermore, the unique
features of photonics (e.g. extreme low-latency, end-to-end transmission, 
high bandwidth
density) have the potential to constitute a discontinuity element able to 
modify the expected
shape of future computer systems from the design point of view and also 
from the
programmability and/or runtime management perspectives.

The AISTECS workshop aims to increase the synergy from a complete range of 
from raw technology issues and solutions up to studies at the overall 
system level of modern
multi-/many-core systems, both from academic and industrial researchers 
working in this
area. We are interested in experimental, systems-related, and 
work-in-progress papers in all
aspects of interconnects in general and SiP technology in particular at 
all levels of

We invite contributions of previously unpublished results on all aspects 
of interconnection
network architectures and SiP that include but are not limited to:
 - Networks on Chip (NoC)
 - Multi-chip interconnection networks, including Cluster Interconnects
 - Communication architectures for 2,5D and 3D stacked systems
 - Switching, buffering, and routing architectures
 - Reconfigurable/programmable interconnect components
 - Photonics in the on-chip and inter-chip interconnections, memory 
hierarchy and I/O of
   computing systems, in future homogeneous/heterogeneous CMPs
 - On-chip and off-chip optical interconnection for HPC systems and 
 - Crucial challenges and design tradeoffs for Silicon Photonics (SiP) in 
future computer
 - Integration of SiP with other technologies
 - Silicon photonics low-level technological improvements and implications 
for computer
   system communication
 - Thermal-/energy- and power-related issues and solutions
 - Asynchronous interconnect designs
 - Interaction with memory hierarchy
 - Architectures for QoS support and coherency
 - Topology exploration
 - Impact of the interconnect on application performance
 - Reliability, availability, fault tolerance
 - Programming models for communication-centric systems
 - Synergies and tradeoffs between photonic and electronic network 


Submitted papers must represent original, previously unpublished, research 
that is not
currently under review for any other workshop, conference or journal. All 
manuscripts will be
reviewed by an international Program Committee and will be judged on 
correctness, originality,
technical strength, significance, quality of presentation, interest, and 
relevance to the workshop
attendees. The submission and review process will be handled 
electronically via EasyChair:

Papers must be in PDF format and should include title, authors and 
affiliations as well as the
e-mail address of the contact author. Papers must be formatted in 
accordance to the
double-column CPS format (http://www.computer.org/web/cs-cps/authors). 
Word and LaTeX
style templates will be available on the website. The workshop encourages 
work-in-progress submissions, with a maximum of six pages for more 
developed work.
Submissions must be limited to six A4 pages, including figures and 
references. Papers
deviating significantly from the paper size and formatting rules may be 
rejected without review.

* Submission deadline: November 2, 2015
* Author notification: November 25, 2015
* Camera-ready paper due: December 4, 2015


The proceedings of the workshop will be published by Conference Publishing 
Services (CPS).
Conference proceedings will be submitted for indexing and inclusion in 
Xplore and CSDL.
Content will be submitted to the indexing companies for possible indexing. 
Indexing services are
independent organizations, and we cannot guarantee that any particular 
abstract or index entry
will be included in Ei Compendex or any other indexing service.


Authors of accepted papers are expected to register for and present their 
papers at the workshop.
Registration will be handled via the HiPEAC Conference.


General Chair:
* Sören Sonntag (Intel, Germany)
* Sandro Bartolini (Università di Siena, Italy)

Program Chairs:
* Giorgos Dimitrakopoulos (Democritus University of Thrace, Greece)
* José M. García (University of Murcia, Spain)

Publication Chair:
* Bogdan Prisacari (IBM Research Zurich, Switzerland)

Web Chair:
* Marco Balboni (University of Ferrara, Italy)

Steering Committee:
* José Duato (Technical University of Valencia, Spain)
* Manolis Katevenis (FORTH, Greece)
* Davide Bertozzi (University of Ferrara, Italy)
* Cyriel Minkenberg (IBM Research Zurich, Switzerland)

Program Committee (to be confirmed):
* Federico Angiolini, iNoCs, Switzerland
* José M. Cecilia, UCAM Murcia, Spain
* Marcello Coppola, STMicroelectronics, France
* Pierfrancesco Foglia, University of Pisa, Italy
* Holger Fröning, University of Heidelberg, Germany
* Francisco Gilabert, Intel, Germany
* Jose Angel Gregorio Monasterio, University of Cantabria, Spain
* Paolo Grani, University of California - St. Davis, USA
* Timothy Jones, University of Cambridge, UK
* Kostas Katrinis, IBM, Ireland
* Sébastien Le Beux, Lyon Institute of Nanotechnology (INL), France
* Hiroki Matsutani, Keio University, Japan
* Gokhan Memik, Northwestern University, USA
* Sergei Mingaleev, VPIphotonics, Germany
* Chrysostomos Nicopoulos, University of Cyprus, Cyprus
* Sudeep Pasricha, Colorado State University, USA
* Nikos Pleros, Aristotle University of Thessaloniki, Greece
* Sven Arne Reinemo, Simula, Norway
* Sebastien Rumley, Columbia University, USA
* Julio Sahuquillo, Universitat Politècnica de València, Spain
* José Luis Sánchez, University of Castilla-La Mancha, Spain
* Laurent Schares, IBM TJ Watson, USA
* Federico Silla, Universitat Politècnica de València, Spain
* Philip M. Watts, University College London, UK
* Eitan Zahavi, Mellanox, Israel
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