[hpc-announce] Deadline Extension — FIFTH WORKSHOP on Data-Flow Execution Models for Extreme Scale Computing (DFM 2015)

Stéphane Zuckerman szuckerm at udel.edu
Wed Sep 2 21:42:18 CDT 2015

   FIFTH WORKSHOP on Data-Flow Execution Models
                for Extreme Scale Computing (DFM 2015)
              to be held in conjunction with PACT 2015
             OCTOBER 18-21, 2015, SAN FRANCISCO, CA, USA


The International workshop on “Data-Flow Models (DFM) for extreme scale
computing” has been held for four consecutive years in conjunction with 
the PACT

The purpose of DFM is to bring together those researchers interested in 
computational models based on Data-Flow principles of execution. The 
switch to
multi-core systems has raised concurrency to the level of a major issue 
if we
are to use the increasing number of cores in a chip.

In the past five decades, sequential computing dominated the computer
architecture landscape because designers were successful at building 
faster and
faster computers by solely relying on improvements on fabrication 
and architectural/organization optimizations. The most severe limitation 
of the
sequential model, namely its inability to tolerate long memory latencies has
slowed down the performance gains. This phenomenon is the ubiquitous Memory
Wall. While various mechanisms have been implemented to overcome the 
memory wall
(such as extremely efficient hardware prefetch support for example), 
they only
add to another wall that hampers highly efficient execution of programs and
modern chip design: the Power Wall. Power considerations and heat 
issues have forced manufacturers to switch to multiple cores per chip 
and thus
move into the concurrency era.

New concurrent models/paradigms are needed in order to fully utilize the
potential of Multi-core chips. The data-flow model is a formal model of
computation that can handle concurrency and tolerate memory and 
latencies. Data-Flow inspired systems could also be simpler and more power
efficient than conventional systems.

Recent work has shown that  data-flow principles can be used to develop 
that can outperform systems based on conventional techniques. Thus, it 
is time
to revisit data-driven computation and bring it to the Multi-core and 
scale computing.

DFM 2015 solicits novel papers that include but are not limited to:

- Novel Data-Flow inspired Execution models and architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and 

All accepted papers will appear in the Computer Society Digital Library

** Important Dates **
Submission Deadline: September 12, 2015
Notification of Authors: September 26, 2015

** Submission URL **

** Steering Committee **
Skevos Evripidou , University of Cyprus, Chair
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo

** Publicity Chair **
Giorgos Matheou, University of Cyprus

** Program Committee **
Stéphane Zuckerman, U. of Delaware Co-chair
Skevos Evripidou, U. of Cyprus  Co-chair
Guang Gao, University of Delaware
Jean-Luc Gaudiot, Univ. of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
John Feo, Pacific Northwest National Lab.
Bob Iannucci, CMU, Silicon Valley, USA
Wallid Najjar, University of California, Riverside
Wolfgang Karl, Karlsruhe Inst. of Technology
Mark Oskin, University of Washington
Andrew Sohn, NJIT, USA
Reiner Hartenstein, TU  Kaiserslautern
Kemal Ebcioğlu, Global Supercomputing Corp.
Roberto Giorgi, University of Siena
Krisha Kavi, University of North Texas

** Proceeding Chair **
Costas Kyriacou, University of Cyprus

Stéphane Zuckerman
University of Delaware, Electrical & Computer Eng. Dept.
Computer Architecture & Parallel Systems Laboratory
201g Evans Hall, Newark,DE 19716 | Work# 3028316534 | Cell# 3028839979

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