[hpc-announce] !!!DEADLINE EXTENSION!!! RAPIDO'16 co-located with HiPEAC Conference
gianluca.palermo at polimi.it
Thu Oct 29 08:14:02 CDT 2015
[Please accept our apologies if you receive multiple copies of this message.]
!!! DEADLINE EXTENDED: Nov. 8 !!!
CALL FOR PAPERS
8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools -
in Prague, Czech Republic, 18 January, 2016
Held in conjunction with the HiPEAC Conference (http://www.hipeac.net/conference)
Confirmed Keynote Speakers:
- Khaled Benkrid, ARM
- Jurgen Teich, University of Erlangen-Nuremberg
- Tim Kogel, Synopsys
Goal of the Workshop :
The focus of the RAPIDO workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance system design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple (heterogeneous) processor cores, multiple levels of (shared/private) caches or memories, and dedicated accelerators, which will be glued together through a network on-chip (NoC).
The design space is huge though and several design metrics should be considered as well for selecting the optimal system configuration. Despite several years of research, the early stage design phase still requires to be supported by innovative design methodologies and tools for simulation, exploartion and performance evaluation. RAPIDO seeks for original research papers that face this challenge for embedded and high performance computing systems.
Topics of interest :
Topics of interest include, but are not limited to:
Rapid simulation techniques targeted at novel architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous Multi-cores/MPSoC, ...
Variability and power/energy consumption in performance estimation and simulation techniques.
High-level abstraction modeling, e.g., Transactional Level Modeling (TLM), Analytical Modeling, Trace-Driven Simulation …
Design space exploration (DSE) for heterogeneous high-performance and embedded systems.
Dynamic binary translation for fast simulation and DSE
Experience reports using existing simulators and tools
Benchmarking and simulator validation
Early stage prototype of innovative architectures
Submission deadline: Nov 8, 2015 (!!!EXTENDED!!!)
Notification to authors: Nov 24, 2015
Final version of accepted papers: Dec 3, 2015
Paper submission :
Electronic paper submission requires a full paper, up to 6 double-column ACM format pages, including figures and references. Up to 2 extra-pages can be requested for free to the organizing commettee (gianluca dot palermo at polimi dot it). Please use the following template when preparing your manuscript: http://www.acm.org/sigs/publications/proceedings-templates
The paper submission will be conducted using the EasyChair conference manager. Papers should be submitted in PDF format. You will find the submission site at: https://easychair.org/conferences/?conf=rapido16
Accepted papers will be published in the ACM digital library.
Gianluca Palermo, Politecnico di Milano
Daniel Gracia Pérez, Thales Research and Technology France
Morteza Biglari-Abhari, University of Auckland
Smail Niar, University of Valenciennes
Daniel Chillet, Université de Rennes 1
Adam Morawiec, ECSI, France
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