[hpc-announce] Call for contributions to ACM TACO 2.0

Koen De Bosschere Koen.DeBosschere at elis.ugent.be
Wed Mar 25 14:59:53 CDT 2015

Do you know ACM TACO 2.0?


Over the last two years ACM TACO (ACM Transactions on Architecture and Code
Optimization,  <http://taco.acm.org/> http://taco.acm.org/) has dramatically
optimized its internal processes. Today, the average turnaround time from
submission to first response is 43 days which is 1.5 months. Most accepted
manuscripts went through two rounds of reviews to reach a final decision
only 5 months after submission. Accepted manuscripts are immediately
published in the ACM digital library. Hence, excellent manuscripts can make
it from submission to the digital library in about 3 months; papers needing
a major revision will make it to the digital library in about 6 months. The
ACM TACO acceptance rate after two review rounds is 27%. We call this “ACM
TACO 2.0”. Attached at the end of this mail are the titles of the papers
printed since January 2015 in ACM TACO.


ACM TACO 2.0 has a review cycle and an acceptance rate which is competitive
with the best ACM conferences, but without the inconvenient non-negotiable
submission deadlines, and with the advantage of being able to revise a paper
based on the detailed review reports by carefully selected reviewers, and of
being published as soon as it is accepted. On top of that, authors of
original work papers get an open invitation to present their paper at the
yearly HiPEAC conference, which is the premier European network event on
topics central to ACM TACO, attended by more than 631 scientists in 2015. We
already have 10 accepted papers for the January 2016 conference in Prague


For the 2014 ACM TACO 2.0 issues, we are calling for high-quality
manuscripts on topics included, but not limited to:

·       Computer system architectures and processor architectures, including
multiprocessors and multithreaded computers

·       Interaction of operating systems, compilers, programming languages,
and architecture

·       Feedback-Directed Software/Hardware Optimization

·       Dynamic compilation, adaptive execution, and continuous

·       Virtual machine, binary translation hardware, and software

·       Compiler optimizations that exploit instruction level parallelism,
such as software pipelining, global scheduling, register allocation, and
memory disambiguation

·       Advanced software and hardware speculation, prediction, and
predication techniques.

·       High-performance microarchitecture innovation (e.g., VLIW,
superscalar, multithreaded, etc.)

·       Architectures and compilers for embedded processors, application
specific processors and DSPs, including network and router architectures

·       Memory system optimization

·       Parallel processing

·       Architecture or compiler-based power and energy optimization

·       Application characterization and architectural implications

·       Performance evaluation and measurement of real systems

·       Papers of interest to the SIGMICRO, SIGARCH, and SIGPLAN community 


There is no deadline but manuscripts are processed on a
first-come-first-served basis. Submit your best work via
<http://mc.manuscriptcentral.com/taco> http://mc.manuscriptcentral.com/taco
as soon as it is ready to go. We will work hard to get back to you in less
than 2 months with your reviews.


Prof. Koen De Bosschere

ACM TACO Editor-in-Chief


Prof. Per Stenström

ACM TACO Senior Associate Editor




Recently published papers 


Volume 11 Issue 4, January 2015


Art 35: Bones: An Automatic Skeleton-Based C-to-CUDA Compiler for GPUs

by Cedric Nugteren, Henk Corporaal 


Art 36: Building and Optimizing MRAM-Based Commodity Memories

by Jue Wang, Xiangyu Dong, Yuan Xie 


Art 37: Revisiting the Complexity of Hardware Cache Coherence and Some

by Rakesh Komuravelli, Sarita V. Adve, Ching-Tsun Chou 


Art 38: Volatile STT-RAM Scratchpad Design and Data Allocation for Low

by Gabriel Rodríguez, Juan Touriño, Mahmut T. Kandemir 


Art 39: Topological Characterization of Hamming and Dragonfly Networks and
Its Implications on Routing

by Cristóbal Camarero, Enrique Vallejo, Ramón Beivide 


Art 40: Efficient Data Mapping and Buffering Techniques for Multilevel Cell
Phase-Change Memories

by Hanbin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur


Art 41: Efficient Out-of-Order Execution of Guarded ISAs

by Nathanael Prémillieu, André Seznec 


Art 42: Automatic and Portable Mapping of Data Parallel Programs to OpenCL
for GPU-Based Heterogeneous Systems

by Zheng Wang, Dominik Grewe, Michael F. P. O’boyle 


Art 43: Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism
with Virtual Blocks

by Dan He, Fang Wang, Hong Jiang, Dan Feng, Jing Ning Liu, Wei Tong, Zheng


Art 44: MAPS: Optimizing Massively Parallel Applications Using Device-Level
Memory Abstraction

by Eri Rubin, Ely Levy, Amnon Barak, Tal Ben-Nun 


Art 45: Improving Multibank Memory Access Parallelism with Lattice-Based

by Alessandro Cilardo, Luca Gallo 


Art 46: The Effects of Parameter Tuning in Software Thread-Level Speculation
in JavaScript Engines

by Jan Kasper Martinsen, Håkan Grahn, Anders Isberg 


Art 47: Studying Optimal Spilling in the Light of SSA

by Quentin Colombet, Florian Brandner, Alain Darte


Art 48: Compiler-Directed Power Management for Superscalars

by Jawad Haj-Yihia, Yosi Ben Asher, Efraim Rotem, Ahmad Yasin, Ran Ginosar


Art 49: Efficient Data Encoding for Convolutional Neural Network application

by Hong-Phuc Trinh, Marc Duranton, Michel Paindavoine


Art 50: Mechanistic Analytical Modeling of Superscalar In-Order Processor

by Maximilien B. Breughe, Stijn Eyerman, Lieven Eeckhout


Art 51: Mitigating Prefetcher-Caused Pollution Using Informed Caching
Policies for Prefetched Blocks

by Vivek Seshadri, Samihan Yedkar, Hongyi Xin, Onur Mutlu, Phillip B.
Gibbons, Michael A. Kozuch, Todd C. Mowry


Art 52: Architectural Support for Data-Driven Execution

by George Matheou, Paraskevas Evripidou


Art 53: GP-SIMD Processing-in-Memory

by Amir Morad, Leonid Yavits, Ran Ginosar


Art 54: The Impact of the SIMD Width on Control-Flow and Memory Divergence

by Thomas Schaub, Simon Moll, Ralf Karrenberg, Sebastian Hack


Art 55: Measuring Microarchitectural Details of Multi- and Many-Core Memory
Systems through Microbenchmarking

by Zhenman Fang, Sanyam Mehta, Pen-Chung Yew, Antonia Zhai, James Greensky,
Gautham Beeraka, Binyu Zang


Art 56: Low-Power High-Efficiency Video Decoding using General-Purpose

by Chi Ching Chi, Mauricio Alvarez-Mesa, Ben Juurlink


Art 57: Cross-Loop Optimization of Arithmetic Intensity for Finite Element
Local Assembly

by Fabio Luporini, Ana Lucia Varbanescu, Florian Rathgeber, Gheorghe-Teodor
Bercea, J. Ramanujam, by by David A. Ham, Paul H. J. Kelly


Art 58: Optimal Parallelogram Selection for Hierarchical Tiling

by Xing Zhou, María J. Garzarán, David A. Padua


Art 59: Making the Most of SMT in HPC: System- and Application-Level

by Leo Porter, Michael A. Laurenzano, Ananta Tiwari, Adam Jundt, William A.
Ward, Jr., Roy Campbell, Laura Carrington


Art 60: Optimizing Memory Translation Emulation in Full System Emulators

by Xin Tong, Toshihiko Koju, Motohiro Kawahito, Andreas Moshovos


Art 61: Compiler/Runtime Framework for Dynamic Dataflow Parallelization of
Tiled Programs

by Martin Kong, Antoniu Pop, Louis-Noël Pouchet, R. Govindarajan, Albert
Cohen, P. Sadayappan


Art 62: Fast Crown Scheduling Heuristics for Energy-Efficient Mapping and
Scaling of Moldable Streaming Tasks on Manycore Systems

by Nicolas Melot, Christoph Kessler, Jörg Keller, Patrick Eitschberger


Art 63: Transactional Read-Modify-Write Without Aborts

by Wenjia Ruan, Yujie Liu, Michael Spear


Art 64: Using Template Matching to Infer Parallel Design Patterns

by Zia Ul Huda, Ali Jannesari, Felix Wolf


Art 65: Efficient Correction of Anomalies in Snapshot Isolation Transactions

by Heiner Litz, Ricardo J. Dias, David R. Cheriton


Art 66: Perfect Reconstructability of Control Flow from Demand Dependence

by Helge Bahmann, Nico Reissmann, Magnus Jahre, Jan Christian Meyer


Art 67: On Using the Roofline Model with Lower Bounds on Data Movement

by Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet,
J. Ramanujam, Radu by by Teodorescu, P. Sadayappan


Volume 12 Issue 1, March 2015 (volume in progress)


Art 1: NoCMsg: A Scalable Message-Passing Abstraction for Network-on-Chips

by Christopher Zimmer, Frank Mueller 


Art 2: Accelerating Divergent Applications on SIMD Architectures Using
Neural Networks

by Beayna Grigorian, Glenn Reinman 


Art 3: Performance-Energy Considerations for Shared Cache Management in a
Heterogeneous Multicore Processor

by Anup Holey, Vineeth Mekkat, Pen-Chung Yew, Antonia Zhai 


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