[hpc-announce] [CFP] IA^3 - DEALINE EXTENDED - August 31

Tumeo, Antonino Antonino.Tumeo at pnnl.gov
Tue Aug 18 16:22:47 CDT 2015

IA^3 2015 - 5th Workshop on Irregular Applications: Architectures and Algorithms
Austin, TX
15 November 2015
To be held in conjunction with SC15
To be held in cooperation with SIGHPC

Call for Papers

Irregular applications span a broad range of applications with unpredictable memory access patterns, control structures, and/or network transfers. They typically use pointer-based data structures such as graphs and trees, often present fine-grained synchronization and communication, and generally operate on very large data sets. They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to tolerate access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as social network analysis, bioinformatics, semantic graph databases, bioinformatics, Computer Aided Design (CAD) and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the scientific challenges of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

*Micro- and System-architectures
*Network and memory architectures
*Heterogeneous, custom and emerging architectures (GPUs, FPGAs, multi- and many-cores, processors-in-memory)
*Modeling, simulation and evaluation of architectures
*Innovative algorithmic techniques
*Parallelization techniques and data structures
*Approaches for managing massive unstructured datasets
*Languages and programming models
*Library and runtime support
*Compiler and analysis techniques
*High performance data analytics, including graph databases

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers.

Important Dates

Abstract submission:                                31 August 2015 11:59 PM PST
Position or full paper submission:             31 August 2015 11:59 PM PST
Notification of acceptance:                        2 October 2015
Camera-ready position and full papers:    9 October 2015
Workshop:                                                 15 November 2015


Submission site: https://easychair.org/conferences/?conf=ia32015

All submissions should be in double-column, single-spaced letter format, using 9-point size fonts, with at least one-inch margins on each side.
The proceedings of the workshop will be published in cooperation with ACM SIGHPC. 
Submitted manuscripts may not exceed eight pages in length for regular papers and four pages for position papers including figures, tables and references.
For any question, please contact the organizers.


Antonino Tumeo, PNNL , antonino.tumeo at pnnl.gov
John Feo, PNNL, Northwest Institute for Advanced Computing, john.feo at pnnl.gov
Oreste Villa, NVIDIA Research, ovilla at nvidia.com

Program Committee 

Scott Beamer, University of California Berkeley, US
David Brooks, Harvard University, US
Vito Giovanni Castellana, Pacific Northwest National Laboratory, US
Georgi Gaydadjiev, Chalmers University, SWE
Maya Gokhale, Lawrence Livermore National Laboratory, US
John Leidel, Texas Tech University, US
Kamesh Madduri, Penn State University, US
Richard Murphy, Micron, US
Onur Mutlu, Carnegie Mellon University, US
Walid Najjar, University of California Riverside, US
Jacob Nelson, University of Washington, US
Kunle Olukotun, Stanford University, US
Timothy Mattson, Intel, US
Gianluca Palermo, Politecnico di Milano, ITA
Fabrizio Petrini, IBM TJ Watson, US
Keshav Pingali, University of Texas Austin, US
Sébastien Rumley, Columbia University, US
Erik Saule, University of Carolina Charlotte, US
John Shalf, Lawrence Berkeley National Laboratory, US
Michela Taufer, University of Delaware, US
Pedro Trancoso, University of Cyprus, CYP

Best Regards,
Antonino Tumeo
Research Scientist
High Performance Computing
Pacific Northwest National Laboratory
antonino.tumeo at pnnl.gov

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