[hpc-announce] Tutorial at DATE 2014 - Wireless NoC as Interconnection Backbone for Multicore Chips

Maurizio Palesi maurizio.palesi at unikore.it
Tue Feb 25 00:47:00 CST 2014

*Tutorial at DATE 2014*

*Wireless NoC as Interconnection Backbone for Multicore Chips: Promises,
Challenges, and Recent Developments


   - Partha Pratim Pande, Washington State University, USA
   - Radu Marculescu, Carnegie Mellon University, USA


   - Radu Marculescu, Carnegie Mellon University, USA
   - Partha Pratim Pande, Washington State University, USA
   - Deukhyoun Heo, Washington State University, USA
   - Hiroki Matsutani, Keio University, Japan

*Abstract: *

Continuing progress and integration levels in silicon technologies make
possible complete end-user systems consisting of extremely high number of
cores on a single chip targeting either embedded or high-performance
computing. However, without new approaches for energy- and
thermally-efficient design, as well as scalable, low power and high
bandwidth on-chip communication architectures, this vision may remain a
pipe dream. Towards this end, wireless Network-on-Chip (WiNoC) represents
an emerging paradigm for designing low power, high bandwidth interconnect
infrastructure for multicore chips. This tutorial will provide a timely and
insightful journey into various challenges and emerging solutions of
designing WiNoC architectures from a variety of different perspectives,
ranging from very high levels of abstraction (e.g., system architecture) to
very low levels (e.g., on-chip antenna and transceiver design).

The tutorial will start by discussing the fundamentals of network-based
communication for 2D and 3D multicore systems and advanced design
techniques for multi-domain clock and power management for embedded and
high-performance processors, using real examples of multicore platforms.

The second part of the tutorial will focus on the design of high bandwidth
and low power WiNoC architectures incorporating the small-world effects. We
will present detailed performance evaluation and necessary design
trade-offs for the small-world WiNoCs with respect to their conventional
wireline counterparts. We will conclude this part of the tutorial by
presenting design of on-chip millimeter (mm)-wave wireless link as the
suitable physical layer for the WiNoCs.

In the last part, we will complement the above discussions regarding planar
WiNoCs by introducing the wireless 3D NoCs that use inductive coupling
though-chip interfaces (TCIs) to connect stacked chips by square coils as
data transmitters. We will present design and implementation of wireless 3D
NoC systems, real-chip experimental results, and their interconnection
techniques. By scope and contents, this tutorial targets students and
researchers belonging to both academia and industry.


9.30: Foundations of On-chip Communication: Performance and Power
Management in 2D and 3D Multicore Platforms.

Author/Speaker: Radu Marculescu, Carnegie Mellon University - USA

10.15: WiNoC: Network Architecture and Communication Resource Management.

Author/Speaker: Partha Pratim Pande, Washington State University - USA

11.00: Coffee Break

11.30: Millimeter-Wave Wireless Link: The Physical Layer Design for WiNoCs.

Author/Speaker: Deukhyoun Heo, Washington State University - USA

12.15: 3D WiNoC Architectures.

Author/Speaker: Hiroki Matsutani, Keio University - Japan
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