[hpc-announce] CFP: 4th Int. Workshop on New Algorithms and Programming Models for the Manycore Era (APMM 2014)
Josef.Weidendorfer at in.tum.de
Wed Feb 12 06:09:22 CST 2014
[We apologize if you receive multiple copies of this message.]
CALL FOR PAPERS
4th International Workshop on New Algorithms and
Programming Models for the Manycore Era
As part of
The International Conference on
High Performance Computing & Simulation (HPCS 2014)
http://hpcs2014.cisedu.info or http://cisedu.us/rp/hpcs14
July 21 – July 25, 2014
The Savoia Hotel Regency
Submission Deadline: March 11, 2014
Submissions can be for full papers, short papers
SCOPE AND OBJECTIVES
With multi- and many-core based systems, performance increase on the
microprocessor side will continue according to Moore's Law, at least
in the near future. However, the already existing performance limitations
due to slow memory access are expected to get worse with multiple cores
on a chip, and complex hierarchies of cache memory will make it hard for
users to fully exploit the theoretically available performance. In
addition, the increasingly hybrid and hierarchical design of compute
clusters and high-end supercomputers, as well as the use of accelerator
components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, Intel SCC, integrated
GPUs etc.) add further challenges to efficient programming in HPC
Therefore, compute and data intensive tasks can only benefit from the
full potential, if both processor and architecture features are taken into
account at all stages - from the early algorithmic design, via appropriate
programming models, up to the final implementation.
The APMM Workshop topics of interest include (but are not limited to)
- Hardware-aware, compute- and memory-intensive simulations of
real-world problems in computational science and engineering
(for example, from applications in electrical, mechanical,
civil, or medical engineering).
- Manycore-aware approaches for large-scale parallel simulations
in both implementation and algorithm design, including scalability
- Parallelisation on HPC platforms; esp. platforms with hierarchical
communication layout, multi-/many-core platforms, NUMA architectures,
or accelerator components (Intel Xeon Phi, NVIDIA and AMD GPU,
FPGA, integrated GPUs (such as AMD APUs or Intel Haswell/Ivy Bridge)).
- Parallelisation with appropriate programming models and tool support
for multi-core and hybrid platforms.
- concepts for exploiting emerging vector extensions of instruction sets
- Software engineering, code optimisation, and code generation strategies
for parallel systems with multi-core processors.
- Tools for performance and cache behavior analysis (including cache
simulation) for parallel systems with multi-core processors.
- Performance modelling and performance engineering approaches for
multi-thread and mutli-process applications.
INSTRUCTIONS FOR PAPER SUBMISSIONS:
You are invited to submit original and unpublished research works on above
and other topics related to Many-core computing. Submitted papers must not
have been published or simultaneously submitted elsewhere. Submission
include a cover page with authors' names, affiliation addresses, fax
phone numbers, and email addresses. Please, indicate clearly the
author and include up to 6 keywords from the above list of topics and an
abstract of no more than 400 words. The full manuscript should be at
pages using the two-column IEEE format. Additional pages will be charged
additional fee. Short papers (up to 4 pages), poster papers and posters
(please refer to http://hpcs2014.cisedu.info/home/posters for the posters
submission details to posters co-chairs) will also be accepted for
Particularly with short papers, we encourage Ph.D. students to submit their
ideas on the workshop topics, even if they have just preliminary results
We would like to provide a forum which allows to discuss their research
In case of multiple authors, an indication of which author(s) is
for correspondence must be indicated. Please include page numbers on all
submissions to make it easier for reviewers to provide helpful comments.
Submit a PDF copy of your full manuscript to the Workshop EasyChair
Acknowledgement will be sent within 48 hours of submission.
Only PDF files will be accepted. Each paper will receive a minimum of
reviews. Papers will be selected based on their originality, relevance,
contributions, technical clarity and presentation. Submission implies the
willingness of at least one of the authors to register and present the
if accepted. Authors of accepted papers must guarantee that their papers
will be registered and presented at the workshop.
Accepted papers will be published in the conference proceedings.
for final manuscript format and requirements will be posted on the HPCS
2014 web site.
It is our intent to have the proceedings formally published in hard and
copies and be available at the time of the conference. The proceedings is
to be published as ISBN proceedings by the IEEE and will be available
through IEEE Digital Library and indexed by major indexing services
(e.g., EI indexing).
If you have any questions about paper submission or the workshop,
please contact the workshop organizers.
Paper Submissions Deadline: ------------------------- March 11, 2014
Acceptance Notification: ---------------------------- April 08, 2014
Camera Ready Papers and Registration Due by: -------- May 06, 2014
Conference Dates: ---------------------------------- July 21 – 25, 2014
WORKSHOP STEERING COMMITTEE
Michael Bader, Technische Universität München, Germany
Alexander Heinecke, Technische Universität München, Germany
Carsten Trinitis, Technische Universität München, Germany
Josef Weidendorfer, Technische Universität München, Germany
Technische Universität München, Germany
Phone: +49 89 289 18619
Fax: +49 89 289 18607
Email: heinecke at in.tum.de
Heriot-Watt University Edinburgh, United Kingdom
Phone: +44 (0) 131 451 3814
Fax: +44 (0)
Email: s.scholz at hw.ac.uk
Dr. Josef Weidendorfer, Informatik, Technische Universität München
TUM I-10 - FMI 01.06.055 - Tel. 089 / 289-18454
More information about the hpc-announce