[hpc-announce] CFP: Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures, Journal of Systems Architecture (JSA)

[Frank Hannig]

*===============================================================================*

                 *    Journal of Systems Architecture (JSA)*
Special Issue on
         *Testing, Prototyping, and Debugging of Multi-Core Architectures*

*===============================================================================*

The steady advances in semiconductor technology allow for increasingly complex SoCs,
including multiple (heterogeneous) micro processors, dedicatedaccelerators, large
on-chip memories, sophisticated interconnection networks,and peripherals. However,
design, verification, and test as well as parallelprogramming of such complex multi-
core architectures are very challenging sincethey may have to deal with highly dynamic
workloads in different applicationscenarios and environments. In addition, the
architecture might alter itself,either intentionally (e.g., dynamic voltage/frequency
scaling, powermanagement) or unintentionally (e.g., failures, aging).One recent
research trend in multi-core computing is to design control loopsacross all platform
layers, from application and run-time software down to thestatus of the underlying
hardware. However, this enhanced flexibility andadaptivity as well as the sheer
complexity of current and future multi-/many-core architectures pose numerous research
questions on how to validate,prototype, and debug such systems. Classical approaches
do not scale (limitedobservability) in the multi-core era as they do not cover new
software andsystem problems related to parallel execution, such as data races or
deadlocks.
This journal special issue will cover recent progress on testing, prototyping, debugging
of multi-core and many-core architectures at all platform layers.Papers with in-depth
and extensive coverage of the following topics are welcome(topics of interest include,
but are not limited to):

  * Testability, prototyping, and debugging of multi-core architectures
  * Debugging problems in multi-cores/many-cores such as concurrency or race conditions
  * Verification and validation of multi-core/many-core architectures
  * Fault tolerance in multi-core systems at hardware and software level
  * Design and test for resource-aware and adaptive systems, self-x properties
  * Resource management, online learning and tuning, and debugging techniques for such
    adaptive systems
  * Debug and test of multi-core predictability (e.g., timing, power, faults, reliability)
  * Reduction of debug and test complexity by increasing software abstraction or
    modular development
  * Novel, scalable debugging tools and prototyping methods for multi-cores
  * Hardware support for software debugging
  * Debug and test for certification
  * Debugging techniques for timing errors



_*SUBMISSION DEADLINE: Sept. 30, 2014*_


_*SUBMISSION INSTRUCTIONS*_

Manuscripts are subject to peer review and should be submitted online at
http://ees.elsevier.com/jsa
When choosing Article Type, please select "SI Multi-Core Testing".
All manuscripts should conform to the standard formats as indicated in the
"Guide for Authors" at
http://www.elsevier.com/journals/journal-of-systems-architecture/1383-7621/guide-for-authors


_*ORGANIZERS*_

*Editor-in-Chief:*
  Iain Bate, University of York, UK

*Guest Editors:*
  Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
  Andreas Herkersdorf, Technische Universität München, Germany
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