[hpc-announce] Call for Participation - Sixth International Workshop on Network on Chip Architectures (NoCArc-13)

Masoud Daneshtalab masdan at utu.fi
Tue Oct 29 12:17:50 CDT 2013

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                                 Call for Participation - NoCArc 2013
         6th IEEE/ACM Int. Workshop on Network on Chip Architectures
                                     To be held in conjunction with
  the 46th Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-46)
                                          December 8th, 2013
                                        Davis, California, USA



Maurizio Palesi and Terrence Mak (General Co-Chairs)

Masoud Daneshtalab (TPC Chair)

General Information

Modern Systems-on-Chip (SoCs) today contains hundreds of Intellectual Properties (IPs)/cores,

including, programmable processors, co-processors, accelerators, application-specific IPs, peripherals,

memories, reconfigurable logic, and even analog blocks. We are now entered in the so called

many-core era. The International Technology Roadmap for Semiconductors foresees that the number

of Processing Elements (PEs) that will be integrated into a SoC will be in the order of thousand

within the 2020. As the number of communicating elements increases, there is a need for an efficient,

scalable and reliable communication infrastructure. As technology geometries shrink to the deep

submicron regime, however, the communication delay and power consumption of global

interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm,

based on a modular packet-switched mechanism, can address many of the on-chip communication

issues such as performance limitations of long interconnects, and integration of large number of

PEs on a chip.

The goal of the workshop is to provide a forum for researchers to present and discuss innovative

ideas and solutions related to design and implementation of many-core systems-on-chip. This

workshop will focus on issues related to design, analysis and testing of on-chip networks.

We also look for new type of NoC-based computing paradigms inspired by biological systems

to solve hard computational problems such as learning, recognition, and complex decision making.

Program (http://www.unikore.it/nocarc/program.html)


December 8th, 2013

08:45-09:00     Workshop Opening

09:00-10:00     Keynote: Millimeter (mm)-Wave Wireless NoC as Interconnection Backbone for

Multicore Chips: Promises and Challenges

Partha Pratim Pande, Washington State University

10:00-10:30     Coffee Break

10:30-12:00     Session I - Network Design

10:30-10:55     On Heterogeneous Network-on-Chip Design Based on Constraint Programming

                        Ayhan Demiriz and Nader Bagherzadeh

10:55-11:20     Design Space Exploration for Streaming Applications on Multiprocessors with

Guaranteed Service NoC

Usman Mazhar Mirza, Flavius Gruian and Krzysztof Kuchcinski

11:20-11:45     Costs and Benefits of Flexibility in Spatial Division Circuit Switched NoC

                        Ahsen Ejaz and Axel Jantsch

11:45-12:00     Empirical and Theoretical Lower Bounds on Energy Consumption for NoC

George Bezerra, Stephanie Forrest and Dorian Arnold

12:00-13:30     Lunch

13:30-15:00     Session II - Routing Algorithms and Topologies

13:30-13:55     LEF: Long Edge First Routing for Two-Dimensional Mesh Network on Chip

                        Ryosuke Sasakawa and Kenji Kise

13:55-14:20     User satisfaction aware routing decisions in NOC

                        Swamy Ponpandi and Akhilesh Tyagi

14:20-14:45     An on-Chip Multicast Supporting Dynamic and Irregular Topology Based on

Dynamic Programming

Wen Zong, Xiaohang Wang and Terrence Mak

14:45-15:00     Towards Optimal Adaptive Routing in 3D NoC with Limited Vertical Bandwidth

                        Gunhee Lee, Jinho Lee and Kiyoung Choi

15:00-15:30     Coffee Break

15:30-16:35     Session III - Emerging Technologies and Modeling

15:30-15:55     Exploiting Emerging Technologies for Nanoscale Photonic Networks-on-Chip

                        Jun Pang, Christopher Dwyer and Alvin R. Lebeck

15:55-16:20     A First Effort for a Distributed Segment-based Approach on Self-Assembled

                        Vincenzo Catania, Andrea Mineo, Salvatore Monteleone and Davide Patti

16:20-16:35     Modeling and Analyzing Timing Faults in Transaction Level SystemC Programs

                        Reza Hajisheykhi, Ali Ebnenasir and Sandeep Kulkarni

16:35-16:45     Closing remarks

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