[hpc-announce] Call for papers: Dataflow Models for Extreme Scale Computing (DFM 2013)

[Stephane Zuckerman]

(Apologies for multiple receptions)

           THIRD WORKSHOP ON DATA-FLOW EXECUTION MODELS
               FOR EXTREME SCALE COMPUTING (DFM 2013)
           to be held in conjunction with PACT 2013

           September 8, 2013, Edinburgh, Scotland
           http://www.cs.ucy.ac.cy/dfmworkshop/

The First International workshop on "Data-Flow Models (DFM) for extreme 
scale computing" was held in Galveston Island, Texas in October 2011 in 
conjunction with PACT 2011. DFM 2012 was held in conjunction with PACT 
2012 in Minneapolis, Minnesota in September 2012.

The purpose of DFM continues being to bring together those researchers 
interested in novel computational models based on Data-Flow principles 
of execution. The switch to multi-core systems has raised concurrency to 
the level of a major issue if we are to use the increasing number of 
cores in a chip.

In the past five decades, sequential computing dominated the computer 
architecture landscape because designers were successful at building 
faster and faster computers by solely relying on improvements on 
fabrication technologies and architectural/organization optimizations. 
The most severe limitation of the sequential model, namely its inability 
to tolerate long memory latencies has slowed down the performance gains. 
This phenomenon is the ubiquitous Memory Wall. While various mechanisms 
have been implemented to overcome the wall (such as extremely efficient 
hardware prefetch support for example), they only add to another wall 
that hampers highly efficient execution of programs and modern chip 
design: the Power Wall. Power considerations and heat dissipation issues 
have forced manufacturers to switch to multiple cores per chip and thus 
move into the concurrency era.

New concurrent models/paradigms are needed in order to fully utilize the 
potential of Multi-core chips. The Data-flow model is a formal model 
that can handle concurrency and tolerate memory and synchronization 
latencies. Data-Flow inspired systems could also be simpler and more 
power efficient than conventional systems. Recent work has shown that 
the Data-Flow principles can be used to develop systems that can 
outperform systems based on conventional techniques. Thus, it is time to 
revisit Data-driven computation and bring it to the Multi-core and 
extreme scale computing.

DFM 2013 solicits novel papers that include but are not limited to:
- Novel Data-Flow inspired Execution models and architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and 
beyond.

All accepted papers will appear in the Computer Society Digital Library. 
Extended versions of the best papers will be published in a special 
issue of IJPP (International Journal on Parallel Programming).

IMPORTANT DATES
Submission Deadline: July 15th
Notification of Authors: Aug 10th

STEERING COMMITTEE
Skevos Evripidou , University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo

PUBLICITY CHAIR
Stéphane Zuckerman, University of Delaware

PROGRAM COMMITTEE
Skevos Evripidou, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, Univ. of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
Kyriacos Stavrou, Intel Labs Barcelona, SP
John Feo, Pacific Northwest National Laboratory
Bob Iannucci, CMU, Silicon Valley, USA
Wallid Najjar, University of California, Riverside
Wolfgang Karl, Karlsruhe Institute of Technology
Mark Oskin, University of Washington
Andrew Sohn, NJIT, USA
Reiner Hartenstein, TU  Kaiserslautern
Kemal Ebcio.lu, Global Supercomputing Corp.

PROCEEDING CHAIRS
Giorgos Michael, University of Cyprus

-- 
Stephane Zuckerman
Computer Architecture and Parallel Systems Laboratory
University of Delaware, 201h Evans Hall Newark. DE 19716
Office # 302 831-6534 / Cell # 302 883 9979


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			THIRD WORKSHOP ON DATA-FLOW EXECUTION MODELS 
				FOR EXTREME SCALE COMPUTING (DFM 2013)
			to be held in conjunction with PACT 2013

				September 8, 2013, Edinburgh, Scotland
				http://www.cs.ucy.ac.cy/dfmworkshop/

The First International workshop on "Data-Flow Models (DFM) for extreme scale computing" was held in Galveston Island, Texas in October 2011 in conjunction with PACT 2011. DFM 2012 was held in conjunction with PACT 2012 in Minneapolis, Minnesota in September 2012.

The purpose of DFM continues being to bring together those researchers interested in novel computational models based on Data-Flow principles of execution. The switch to multi-core systems has raised concurrency to the level of a major issue if we are to use the increasing number of cores in a chip. 

In the past five decades, sequential computing dominated the computer architecture landscape because designers were successful at building faster and faster computers by solely relying on improvements on fabrication technologies and architectural/organization optimizations. The most severe limitation of the sequential model, namely its inability to tolerate long memory latencies has slowed down the performance gains. This phenomenon is the ubiquitous Memory Wall. While various mechanisms have been implemented to overcome the wall (such as extremely efficient hardware prefetch support for example), they only add to another wall that hampers highly efficient execution of programs and modern chip design: the Power Wall. Power considerations and heat dissipation issues have forced manufacturers to switch to multiple cores per chip and thus move into the concurrency era.

New concurrent models/paradigms are needed in order to fully utilize the potential of Multi-core chips. The Data-flow model is a formal model that can handle concurrency and tolerate memory and synchronization latencies. Data-Flow inspired systems could also be simpler and more power efficient than conventional systems. Recent work has shown that the Data-Flow principles can be used to develop systems that can outperform systems based on conventional techniques. Thus, it is time to revisit Data-driven computation and bring it to the Multi-core and extreme scale computing.

DFM 2013 solicits novel papers that include but are not limited to:
- Novel Data-Flow inspired Execution models and architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and beyond.

All accepted papers will appear in the Computer Society Digital Library. Extended versions of the best papers will be published in a special issue of IJPP (International Journal on Parallel Programming).

IMPORTANT DATES
Submission Deadline: July 15th
Notification of Authors: Aug 10th

STEERING COMMITTEE
Skevos Evripidou , University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo

PUBLICITY CHAIR
Stéphane Zuckerman, University of Delaware

PROGRAM COMMITTEE
Skevos Evripidou, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, Univ. of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
Kyriacos Stavrou, Intel Labs Barcelona, SP
John Feo, Pacific Northwest National Laboratory
Bob Iannucci, CMU, Silicon Valley, USA
Wallid Najjar, University of California, Riverside
Wolfgang Karl, Karlsruhe Institute of Technology
Mark Oskin, University of Washington
Andrew Sohn, NJIT, USA
Reiner Hartenstein, TU  Kaiserslautern
Kemal Ebcio.lu, Global Supercomputing Corp.

PROCEEDING CHAIRS
Giorgos Michael, University of Cyprus