[hpc-announce] DEADLINE EXTENSION: CFP: APMM 2013 - 3rd Int. Workshop on New Algorithms and Programming Models for the Manycore Era

Josef Weidendorfer Josef.Weidendorfer at in.tum.de
Fri Mar 1 09:37:04 CST 2013

*** Apologies if you receive multiple copies. ***
*** Please forward to interested colleagues.  ***


                              CALL FOR PAPERS

   3rd International Workshop on New Algorithms and Programming Models
                     for the Manycore Era (APMM 2013)

                           As part of HPCS 2013,
     The 2013 Int. Conf. on High Performance Computing & Simulation

                     July 1-5, 2013, Helsinki, Finland



NEW EXTENDED Submission Deadline: March 9, 2013
Submissions can be for full papers or short papers!


With multi- and many-core based systems, performance increase on the
microprocessor side will continue according to Moore's Law, at least in
the near future.  However, the performance limitations due to slow
memory access are getting worse with large numbers of cores on a chip,
and complex hierarchies of cache memory makes it hard for users to fully
exploit the theoretically available performance.  In addition, the
increasingly hybrid and hierarchical design of compute clusters and
high-end supercomputers, as well as the use of accelerator components
(GPGPUs, Intel MIC, etc.) add further challenges to efficient
programming in HPC applications.
Compute and data intensive tasks can only benefit from the hardware's
full potential, if both processor and architecture features are taken
into account at all stages - from the early algorithmic design, via
appropriate programming models, up to the final implementation.

The Workshop topics of interest include (but are not limited to) the

* Hardware-aware, compute- and memory-intensive simulations of
   real-world problems in computational science and engineering (for
   example, from applications in electrical, mechanical, civil, or
   medical engineering).

* Manycore-aware approaches for large-scale parallel simulations in both
   implementation and algorithm design, including scalability studies.

* Parallelisation on HPC platforms; esp. platforms with hierarchical
   communication layout, multi-/many-core platforms, NUMA architectures,
   or accelerator components (Intel MIC, GPU, Tilera, FPGA).

* Parallelisation with appropriate programming models and tool support
   for multi-core and hybrid platforms.

* Concepts for exploiting emerging vector extensions of instruction sets

* Software engineering, code optimisation, and code generation
   strategies for parallel systems with multi-core processors.

* Tools for performance and cache behavior analysis (including cache
   simulation) for parallel systems with multi-core processors.

* Performance modelling and peformance engineering approaches for
   multi-thread and mutli-process applications.


You are invited to submit original and unpublished research works on
above and other topics related to Many-core computing.  Submitted papers
must not have been published or simultaneously submitted elsewhere.
Submission should include a cover page with authors' names, affiliation
addresses, fax numbers, phone numbers, and email addresses.  Please,
indicate clearly the corresponding author and include up to 6 keywords
from the above list of topics and an abstract of no more than 400 words.
The full manuscript should be at most 7 pages using the two-column IEEE
format.  Additional pages will be charged additional fee.  Please
include page numbers on all preliminary submissions to make it easier
for reviewers to provide helpful comments.

Submit a PDF copy of your full manuscript via EasyChair:

Only PDF files will be accepted, sent by email to the workshop
organizers.  Each paper will receive a minimum of three reviews. Papers
will be selected based on their originality, relevance, technical
clarity and presentation.  Submission implies the willingness of at
least one of the authors to register and present the paper, if
accepted. Authors of accepted papers must guarantee that their papers
will be registered and presented at the workshop.

Accepted papers will be published in the Conference proceedings.
Instructions for final manuscript format and requirements will be
posted on the HPCS 2013 Conference web site.  It is our intent to have
the proceedings formally published in hard and soft copies and be
available at the time of the conference.  The proceedings is projected
to be included in the IEEE Digital Library and indexed accordingly.

If you have any questions about paper submission or the workshop,
please contact the workshop organizers.


   Paper Submissions: ------------------------ March 09, 2013
   Acceptance Notification: ------------------ March 15, 2013
   Camera Ready Papers and Registration Due: - April 11, 2013
   Conference Dates:  ------------------------ July 1-5, 2013


Alexander Heinecke, Technische Universitaet Munich, DE
Harald Koestler, University Erlangen-Nuremberg, DE
Sven-Bodo Scholz, Heriot-Watt University Edinburgh, UK


Michael Bader, TUM, DE
Josef Weidendorfer, TUM, DE
Carsten Trinitis, TUM, DE
Alexander Heinecke, TUM, DE


(see web site for an updated list of IPC members)


See the Workshop web site at

HPCS 2013

For information or questions about Conference's paper submission,
tutorials, posters, workshops, special sessions, exhibits, demos,
panels and forums organization, doctoral colloquium, and any other
information about the conference location, registration, paper
formatting, etc., please consult the Conference’s web site at
http://hpcs2013.cisedu.info or contact one of the Conference's

If you have any questions about the HPCS 2013 conference paper
submission, please contact the

  Conference Program Chair: Waleed W. Smari
  Voice: +1 (937) 681-0098, Email: smari at arys.org

Dr. Josef Weidendorfer, Informatik, Technische UniversitÀt MÌnchen
TUM I-10 - FMI 01.06.055 - Tel. 089 / 289-18454

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