[hpc-announce] CFPs: Track on INterconnect ARchitectures for Reconfigurable Computing Systems at ReConFig 2013

anrope2 anrope2 at gap.upv.es
Wed Jun 26 09:31:35 CDT 2013

(apologies if you receive multiple copies)


                                           CALL FOR PAPERS

                                        INARCS at ReConFig

         Track on INterconnect ARchitectures for Reconfigurable 
Computing Systems
  To be held at International Conference on ReConFigurable Computing and 
FPGAs (ReConFig 2013)

                              Cancun, Mexico, 9-11 December




The increase in performance and capacity of modern FPGAs enable the 
design of on-FPGA multiprocessing SoC. The efficient operation of such 
systems and their fast integration require efficient on-chip 
communication fabrics called networks-on-fpgas. Current knowledge and 
research in interconnects can not directly be applied to FPGA domain, as 
suboptimal solutions will be achieved. There is a need of a customized 
design of the network tailored to the FPGA constraints and opportunities 
it brings. Optimal implementations can be supported by hard pre-built 
network components that will simplify design and increase performance of 
overlaid soft interconnect architectures.
At the same time, the emerging high-performance reconfigurable computing 
systems that aim in integrating thousands of FPGA nodes, require novel 
system interconnect architectures with both on-chip and off-chip 
components. The increasing IO bandwidth of FPGA fabrics enable truly 
scalable interconnect architectures that would fit the novel programming 
models, the communication patterns and the accelerator-rich features of 
Reconfigurable HPC systems.
The emergence of such interconnect architectures with both hard and soft 
components is expected to inspire new designs, specially when dealing 
with reconfigurable systems. There is a need to identify the best 
designs and practices combining all the solutions provided. For example: 
(1) the intrinsic reconfiguration capabilities of FPGAs and/or 
in-network reconfiguration capabilities for on-chip interconnects, (2) 
network-centric reconfiguration protocols and/or paralelized 
reconfiguration operations, and (3) additional properties such as 
isolation, partitioning and virtualization.
This track aims to create a forum for researchers from both environments 
(interconnects and reconfigurable computing systems) to come up with 
efficient solutions and approaches for reconfigurable FPGA-based 
interconnect systems and identifying the potential of such 
inter-disciplinary concept.

TOPICS OF INTEREST (not limited to)

- Hard and Soft interconnect architectures
- Customized networks-on-fpgas
- Interconnect architectures and protocol for reconfigurable HPC systems
- Network-centric reconfiguration mechanism
- Interconnect fault-tolerant techniques
- Virtualization/partitioning support of the interconnect
- In-network cache coherence support
- Hands-on experiences on interconnects embedded in FPGA systems


Conference proceedings will be published by IEEE and will appear at the 
IEEE Digital Library (IEEE Xplore). Authors of selected papers will be 
invited to submit an extended version for publication in ReConFig'13 
Special Issues of international journals (TBC).


Submissions should be no more than 6 pages long including tables, 
figures and references (4 pages for PhD Forum). They have to be 
submitted for evaluation as a PDF file using IEEE formatting (US-letter 

Additional pages can be purchased for regular papers at a price of 75 
USD per page (up to 2 extra pages are allowed). No additional pages will 
be allowed for PhD forum papers.

At least one author of every submitted paper has to attend the 
conference if the paper is accepted. Authors who do not attend the 
conference to present their papers will not have their paper published 
in the conference´s proceedings.


Paper submission:                 19   July      2013
Notification of acceptance:  13   September 2013
Final paper submission:       15   October   2013
Conference:                           9-11 December  2013



  * Jose Flich  (Universidad Politécnica de Valencia, Spain)
  * Giorgos Dimitrakopoulos (Democritus University of Thrace, Greece)
  * Antoni Roca (Universidad Politécnica de Valencia, Spain)

Program Committee:

  * Yannis Papaefstathiou (University of Crete, Greece)
  * Pedro Gil (Universidad Politécnica de Valencia, Spain)
  * Ioannis Sourdis (Chalmers University of Technology, Sweden)
  * Teresa Riesgo (Universidad Politécnica de Madrid, Spain)
  * Gerard K. Rauwerda (Recore Systems, Netherlands)
  * Hiroki Matsutani (Keio University, Japan)
  * Vaughn Betz (University of Toronto, Canada)
  * Andreas Doering (IBM Research, Zurich)
  * Felix Tobajas (Universidad de las Palmas de Gran Canaria, Spain)
  * Terrence Mak (The Chinese University of Hong Kong, Hong Kong)
  * Elliot Fleming (Intel, USA)
  * Christoforos Kachris (Athens Information Technology, Greece)


For more information on INARCS 2013 (special track held on ReConFig'13) 
or if you have any questions please contact the special track organizers 
at inarcs2013 at gap.upv.es

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