[hpc-announce] HEART 2014 CFP: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

Miriam Leeser mel at coe.neu.edu
Mon Dec 30 15:32:34 CST 2013

(apologies if you receive multiple HEART publicity emails)



  International Symposium on
  Highly Efficient Accelerators and Reconfigurable Technologies
  9-11 June 2014 @ Sendai Miyagi, Japan

  Important Dates:

  Important dates (all 23:59 UTC+0):
  - Paper submission: February 21, 2014
  - Author notification: April 11, 2014


The 5th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies (HEART) is a forum to present
and discuss new researches on accelerators and the use of
reconfigurable technologies for high-performance and/or
power-efficient computation. Submissions are solicited on
a wide variety of topics related to the acceleration for
high-performance computation, including but not limited to:

[Architectures and systems]:
- Novel systems/platforms for efficient acceleration
   based on FPGA, GPU, and other devices
- Heterogeneous processor architectures and systems for scalable,
   high-performance, high-reliability, and/or low-power computation
- Reconfigurable and configurable hardware and systems including
   IP-cores, embedded systems, SoCs, and cluster/grid/cloud
   computing systems for scalable, high-performance and/or
   low-power processing
- Custom computing systems for domain-specific applications
   such as Big-data, multimedia, bioinformatics, cryptography, and more
- Novel architectures and device technologies that can be applied
   to efficient acceleration, including many-core/NoC architectures,
   3D-stacking technologies and optical devices

[Software and applications]:
- Novel applications of high-performance computing and Big-data
   processing with efficient acceleration and custom computing
- System software, compilers and programming languages for efficient
   acceleration systems / platforms, including many-core processors,
   GPUs, FPGAs and other reconfigurable /custom processors
- Run-time techniques for acceleration, including Just-in-Time
   compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous,
   reconfigurable and/or custom processors/systems

In order to encourage open discussion on future directions, the
program committee will provide higher priority for papers that
present highly innovative and challenging ideas.

As in previous HEART editions, we plan to publish selected
accepted papers at HEART 2014 in post-proceedings ACM SIGARCH
Computer Architecture News (CAN), which is also available in
ACM Digital Library.

Prospective authors are invited to submit original and unpublished
contributions as 6-page papers to be considered as regular papers
or 4-page papers to be considered as poster papers. All contributions
must be submitted electronically in PDF format (two columns,
US letter size, single-spacing, 10 points for main body text).
For double-blind review, manuscripts must NOT identify the authors
in any way, so author names, affiliations, e-mail addresses and
self-references should be blanked out. Papers that identify authors
may be rejected without review. You can submit your contribution(s)
by following this easychair submission link,

Each accepted paper MUST have at least one author with a regular
registration for the manuscript to be included and published in
the symposium proceedings and ACM SIGARCH CAN post-proceedings.
Authors are also expected to attend and present their paper(s)
at the symposium.

Important dates (all 23:59 UTC+0):
- Paper submission: February 21, 2014
- Author notification: April 11, 2014
- Camera-ready due: April 25, 2014
- Symposium Dates: June 9-11, 2014

[FPGA Design Contest 2014 (Blocus Duo Revenge)]
Following the FPGA design competition in ICFPT2013, we are planning
another Blokus Duo design contest at HEART2014. The regulation of
this contest is slightly different from that of ICFPT2013; the new
regulation reduces the first-move advantage in the previous
regulation. To get more information, please visit:

Organizing Committee
General chair:
     Hideharu Amano, Keio University, JP
Vice co-chairs:
     Martin Herbordt, Boston University, US
     Kentaro Sano, Tohoku University, JP
Technical program co-chairs:
     Toshihiro Hanawa, University of Tokyo, JP
     Hayden Kwok-Hay So, the University of Hong Kong, HK
     Lesley Shannon, Simon Fraser University, CA
Publicity co-chairs:
     Miriam Leeser, Northeastern University, US
     David Thomas, Imperial College London, UK
     Yoshiki Yamaguchi, University of Tsukuba, JP
Special session co-chairs:
     Masanori Hariyama, Tohoku University, JP
     Michael Hubner, Karlsruhe Institute of Technology, DE
     Hiroyuki Takizawa, Tohoku University, JP
Finance chair:
     Yukinori Sato, JAIST, JP
Publication co-chairs:
     Hironori Nakajo, Tokyo University of Agriculture and Technology, JP
     Yuichiro Shibata, Nagasaki University, JP
Exihition chair:
     Ryusuke Egawa, Tohoku University, JP
Industrial co-chiars:
     Hiroaki Inoue, NEC Green Platform Research Labs, JP
     Khaled Benkrid, ARM, UK
Design contest co-chairs:
     Yasunori Osana, University of the Ryukyus, JP
Local arrangement co-chairs:
     Hasitha Waidyasooriya, Tohoku University, JP
     Tomohiro Ueno, Tohoku University, JP

Program Committee (TBD)
     Ali Akoglu, University of Arizona, US
     Jason Anderson, University of Toronto, CA
     Samuel Bayliss, Imperial College London, UK
     Ray C.C. Cheung, City University of Hong Kong, HK,
     Florent de Dinechin, Ecole Normale Superieure de Lyon, FR
     Diana Goehringer, Karlsruhe Institute of Technology, DE
     Guy Gogniat, Universite de Bretagne-Sud, Fr
     Gary Grewal, University of Guelph, CA
     Yajun Ha, National University of Singapore, SG
     Masanori Hashimoto, Osaka University, JP
     Brad Hutchings, Brigham Young University, US
     Tomonori Izumi, Ritsumeikan University, JP
     Peter Andrew Jamieson, Miami University, US
     Qiwei Jin, Imperial College, London, UK
     Nachiket Kapre, Nanyang Technological University, SG
     Kenneth B. Kent, University of New Brunswick, CA
     Joo-Young Kim, Microsoft Research, US
     Dirk Koch, University of Manchester, UK
     Herman Lam, University of Florida, US
     Philip Leong, University of Sydney, AU
     Tsutomu Maruyama, University of Tsukuba, JP
     Zaltan Nagy, Hungarian Academy of Sciences, HU
     Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
     Gregory Peterson, University of Tennessee, US
     Ioannis Sourdis, Chalmers University of Technology, SE
     Henry Styles, Xilinx, US
     Bharat Sukhwani, IBM T. J. Watson Research Center, US
     Thomas D. VanCourt, Akamai Technologies, US
     Wim Vanderbauwhede, University of Glagow, UK
     Tanya Vladimirova, University of Leicester, UK
     Tao Wang, Peking University, CN
     Yu Wang, Tsinghua University, CN
     Minoru Watanabe, Shizuoka University, JP
     Stephan Wong, Delft University of Technology, NL
     Masato Yoshimi, Doshisha University, JP

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