[hpc-announce] DEADLINE EXTENDED - IA^3 2012

[Tumeo, Antonino]

**** Apologies if you receive multiple copies of this CFP ****

Please, note the EXTENDED DEADLINE until  - SEPTEMBER 17 -

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IA^3 Workshop on Irregular Applications: Architectures & Algorithms
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http://cass-mt.pnnl.gov/irregularworkshop.aspx
Sunday, November 11, 2012
Salt Lake City, UT USA

To be held in conjunction with:
SC12 - The International Conference for High Performance Computing, Networking, Storage and Analysis
http://sc12.supercomputing.org<http://sc12.supercomputing.org/>

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THEME
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Many data intensive scientific applications are by nature irregular. They may present irregular data structures, control flow or communication. Current supercomputing systems are organized around components optimized for data locality and regular computation. Developing irregular applications on them demands a substantial effort, and often leads to poor performance. However, solving these applications efficiently will be a key requirement for future systems.

The solutions needed to address these challenges can only come by considering the problem from all perspectives: from micro- to system-architectures, from compilers to languages, from libraries to runtimes, from algorithm design to data characteristics. Only collaborative efforts among researchers with different expertise, including end users, domain experts, and computer scientists, could lead to significant breakthroughs. This workshop aims at bringing together scientists with all these different backgrounds to discuss, define and design methods and technologies for efficiently supporting irregular applications on current and future architectures.

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CALL FOR PAPERS
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Irregular applications span a broad range of applications with unpredictable memory access patterns, control structures, and/or network transfers. They typically use pointer-based data structures such as graphs and trees, often present fine-grained synchronization and communication, and generally operate on very large data sets. They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to tolerate access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as Computer Aided Design (CAD), bioinformatics, semantic graph databases, social network analysis, and computer security. Addressing the issues of these applications on current and future architectures will become critical to solve the scientific challenges of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

* Micro- and System-architectures
* Network and memory architectures
* Manycore, heterogeneous and custom architectures (Tilera, GPUs, FPGAs)
* Modeling and evaluation of architectures
* Innovative algorithmic techniques
* Parallelization techniques and data structures
* Languages and programming models
* Library and runtime support
* Compiler and analysis techniques

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers.

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IMPORTANT DATES
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* Paper Submission: 17 September 2012 (23:59 PST) - EXTENDED!!!!
* Notification of acceptance: 5 October 2012
* Workshop: 11 November 2012

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PAPER SUBMISSION GUIDELINES
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Submission site: http://www.easychair.org/conferences/?conf=ia3-2012

All submissions should be in double-column, single-spaced letter format, using 10-point size fonts, with at least one inch margins on each side. Submitted manuscripts may not exceed eight pages in length for regular papers and four pages for position papers including figures, tables and references. For any question, please contact the organizers.

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ORGANIZERS
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* Antonino Tumeo, PNNL (antonino.tumeo at pnnl.gov<mailto:antonino.tumeo at pnnl.gov>)
* Oreste Villa, PNNL (oreste.villa at pnnl.gov<mailto:oreste.villa at pnnl.gov>)
* John Feo, PNNL (john.feo at pnnl.gov<mailto:john.feo at pnnl.gov>)
* Mahantesh Halappanavar, PNNL (mahantesh.halappanavar at pnnl.gov<mailto:mahantesh.halappanavar at pnnl.gov>)
* Simone Secchi, Università di Cagliari (simone.secchi at diee.unica.it<mailto:simone.secchi at diee.unica.it>)

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PROGRAM COMMITTEE
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David Bader, Georgia Institute of Technology (USA)
David Brooks, Harvard University (USA)
Bryan Catanzaro, NVIDIA (USA)
Daniel Chavarria, PNNL (USA)
Jonathan Cohen, NVIDIA (USA)
Georgi Gaydadjiev, Chalmers University of Technology (SWE)
Roberto Gioiosa, PNNL (USA)
Matteo Monchiero, Intel (USA)
Walid Najjar, University of California Riverside (USA)
Jacob Nelson, University of Washington (USA)
Kunle Olukotun, Stanford University (USA)
Gianluca Palermo, Politecnico di Milano (ITA)
John Shalf, LBNL (USA)
Cristina Silvano, Politecnico di Milano (ITA)
Pedro Trancoso, University of Cyprus (CYP)
Mateo Valero, Barcelona Supercomputing Center (ESP)