[hpc-announce] CFP 5th Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)
gpalermo at elet.polimi.it
Mon Sep 10 09:39:05 CDT 2012
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CALL FOR PAPERS & POSTERS
5th Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools
in Berlin, Germany, January 21, 2013
Held in conjunction with the 8th International Conference on High
Performance Embedded Architectures and Compilers (HiPEAC)
- Goal of the Workshop :
The focus of the RAPIDO’13 workshop is on methods and tools for rapid
simulation and performance evaluation in embedded and high performance
system design. Given continuous advances in chip technology, it is to
be expected that future-generation processors will integrate numerous
units on a single die, including multiple processor cores, multiple
levels of (shared/private) caches or memories, and multiple dedicated
accelerators, which will be glued together through a network on-chip
The design space is huge though:
How many cores do we need?
Should we have a homogeneous or a heterogeneous design?
When dynamic reconfiguration must be performed?
How many caches/memories do we need?
How to choose the instruction set(s) for these cores?
What are the best code optimizations for a given application?
How to combine the different metrics (e.g. energy, latency and
throughput) into a global search space?
- Topics of interest :
Topics of interest include, but are not limited to:
Rapid simulation techniques especially those targeted at new
architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous
Variability and power/energy consumption in performance estimation and
High-level abstraction modeling, e.g., Transactional Level Modeling
(TLM), Analytical Modeling, Trace-Driven Simulation …
Rapid design space exploration (DSE) for heterogeneous and embedded systems.
Dynamic binary translation for fast simulation and DSE
Experience reports using existing simulators
Benchmarking and simulator validation
- Invited speakers:
Pascal Vivet, Commissariat à l’Energie Atomique, France: (Talk title
to be defined)
Emre Ozer, ARM, UK: (Talk title to be defined)
Mike Ferdman, Stony Brook University, USA: (Talk title to be defined)
(more invited speakers to be defined)
- Important dates:
Submission deadline: Oct 22, 2012
Notification to authors: Nov 21, 2012
Final version of accepted papers: Dec 5, 2012
Poster submission deadline: Dec 16, 2012
Poster notification to authors: Dec 20, 2012
- Paper submission :
Electronic paper submission requires a full paper, up to 8
double-column ACM format pages, including figures and references.
Please use the following template when preparing your manuscript:
The paper submission will be conducted using the EasyChair conference
manager. Papers should be submitted in PDF format.
You will find the submission site at:
Accepted papers will be published in the ACM digital library.
- Poster submission :
In addition to the poster session (held in conjunction with the HiPEAC
conference), there will be a short presentation time for introducing
the posters during the workshop. Poster submissions should either be a
150-200 word abstract or in the form of the poster itself (in an A4 or
US Letter size format) and should clearly relate to the workshop
goals/topics. A workshop digest based upon the one-page abstract and
one-page poster will be distributed to all participants of the
workshop. Note that the posters presented at the RAPIDO workshop are
NOT disseminated through any formal channels, such as, for example,
the IEEExplore or the ACM Digital Library.
Posters will be published online at the Workshop web site:
You will find the submission site at:
- Program Committee:
Jerónimo Castrillon, Aachen University of Technology, Germany
Ahmed Jerraya, CEA, France
Tim Kogel, Synopsys Gmbh, Germany
Tulika Mitra, National University of Singapore, Singapore
Ozkan Orturk, Bilkent University, Turkey
Mazen Saghir, Texas A&M University, Qatar
Victor Moya del Barrio, Universitat Politècnica de Catalunya, Spain
Michael Hübner, Ruhr-Universität Bochum, Germany
Mario Porrmann, University of Paderborn, Germany
Jari Nurmi, Tampere University of Technology, Finland
Pierre Boulet, University of Lille/INRIA, France
Sami Yehia, Intel, USA
Daniel Gracia Pérez, Thales Research and Technology France, France
Morteza Biglari-Abhari, University of Auckland, New Zealand
Gianluca Palermo, Politecnico di Milano, Italy
Daniel Chillet, Université de Rennes 1, France
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