[hpc-announce] Extended Deadline: Workshop on Large-Scale Parallel Processing (LSPP'10)

[Darren]

[Please accept our apologies if you receive multiple copies]

-----------------------------------------------------------------
Call for papers:      Workshop on LARGE-SCALE PARALLEL PROCESSING

               to be held in conjunction with
IEEE International Parallel and Distributed Processing Symposium    
                      Atlanta, Georgia
                      April 23rd, 2010

EXTENDED DEADLINE:  December 18th  2009 (Final)

Selected work presented at the workshop will be published in a
special issue of Parallel Processing Letters.
-----------------------------------------------------------------

The workshop on Large-Scale Parallel Processing is a forum that
focuses on computer systems that utilize thousands of processors
and beyond. This is a very active area given the goals of many
researchers world-wide to enhance science-by-simulation through
installing large-scale multi-petaflop systems at the start of
the next decade. Large-scale systems, referred to by some as
extreme-scale and Ultra-scale, have many important research
aspects that need detailed examination in order for their
effective design, deployment, and utilization to take place.
These include handling the substantial increase in multi-core on
a chip, the ensuing interconnection hierarchy, communication, and
synchronization mechanisms. The workshop aims to bring together
researchers from different communities working on challenging
problems in this area for a dynamic exchange of ideas. Work at
early stages of development as well as work that has been
demonstrated in practice is equally welcome.

Of particular interest are papers that identify and analyze novel
ideas rather than providing incremental advances in the following
areas:

- LARGE-SCALE SYSTEMS : exploiting parallelism at large-scale,
  the coordination of large numbers of processing elements,
  synchronization and communication at large-scale, programming
  models and productivity

- MULTI-CORE : utilization of increased parallelism on a single
  chip (MPP on a chip such as the Cell and GPUs), the possible
  integration of these into large-scale systems, and dealing with
  the resulting hierarchical connectivity.

- NOVEL ARCHITECTURES AND EXPERIMENTAL SYSTEMS : the design of
  novel systems, the use of processors in memory (PIMS),
  parallelism in emerging technologies, future trends.

- APPLICATIONS : novel algorithmic and application methods,
  experiences in the design and use of applications that scale to
  large-scales, overcoming of limitations, performance analysis
  and insights gained.

Results of both theoretical and practical significance will be
considered, as well as work that has demonstrated impact at
small-scale that will also affect large-scale systems. Work may
involve algorithms, languages, various types of models, or
hardware.

-----------------------------------------------------------------
SUBMISSION GUIDELINES

Papers should not exceed eight single-space pages (including
figures, tables and references) using a 12-point font on 8.5x11
inch pages. Submissions in PostScript or PDF should be made
using EDAS (www.edas.info). Informal enquiries can be made to
djk at lanl.gov. Submissions will be judged on correctness,
originality, technical strength, significance, presentation
quality and appropriateness. Submitted papers should not have
appeared in or under consideration for another venue.

IMPORTANT DATES

Submission deadline:         December 18th  2009 (Final)
Notification of acceptance:  January  15th  2010
Camera-Ready Papers due:     February  1st  2010

-----------------------------------------------------------------
WORKSHOP CO-CHAIRS

Darren J. Kerbyson      Los Alamos National Laboratory
Ram Rajamony            IBM Austin Research Lab
Charles Weems           University of Massachusetts

STEERING COMMITTEE

Johnnie Baker           Kent State University
Alex Jones              University of Pittsburgh
H.J. Siegel             Colorado State University

PROGRAM COMMITTEE

Ghoerge Almasi          IBM T.J. Watson Research Lab
Taisuke Boku            University of Tsukuba, Japan
Marco Daneluto          University of Pisa
Martin Herbordt         Boston University
Lei Huang               University of Houston
Daniel Katz             University of Chicago
Jesus Labarta           Barcelona Supercomputer Center, Spain
John Michalakes         NCAR, Boulder
Celso Mendes            University of Illinois Urbana-Champagne
Bernd Mohr              Forschungszentrum Juelich, Germany
Stathis Papaefstathiou  Microsoft
Michael Scherger        Texas A&M University-Corpus Christi
Harvey Wasserman        NERSC/LBNL
Gerhard Wellein         University of Erlangen, Germany
Pat Worley              Oak Ridge National Laboratory

Workshop Webpage: http://www.ccs3.lanl.gov/LSPP